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We need Hard Debug. I mark MII pins from the RMII to MII wrapper for debugging. In Vivado analyzer I see MAC addresses in the MII RX Data bus, hence the packets do get into FPGA and do get converter converted from RMII to MII also. So where is the problem?
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Lets take out network cable, and reset this bit, now it stays 0. Cable back, reading again. And again the buffer valid bit goes 1.
So why id did LwIP never see any incoming packets?
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