Page History

Additional HW Requirements:

Prebuilt

Content

• content of the zip file

For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources

Additional Sources

Prebuilt

• • Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File Boot Source *.scr Distro Boot file DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface Debian SD-Image *.img Debian Image for SD-Card Diverse Reports --- Report files in different formats Hardware-Platform-Description-File *.xsa Exported Vivado hardware description file for Vitis and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File MCS-File *.mcs Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) MMI-File *.mmi File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems SREC-File *.srec Converted Software Application for MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0??? "Test Board" Reference Design

Design Flow

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• AM0010 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Xilinx Development Tools
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   Code Block
   language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Xilinx Development Tools
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   Code Block
   language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh
   ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- ----------Set design paths---------------------------- ------- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> ----------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

2. Press 0 and enter to start "Module Selection Guide"
Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.


3. ------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

   
   

4. Press 0 and enter to start "Module Selection Guide"
5. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
   

   • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note
     Note: Select correct one, see also Vivado Board Part Flow

     
     

6. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

Note
Note: Select correct one, see also Vivado Board Part Flow

Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

Code Block
language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
TE::hw_build_design -export_prebuilt

Info
Using Vivado GUI is the same, except file export to prebuilt folder.

7. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the "<plnx-proj-root>/images/linux" directory

8. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
   

9. Copy PetaLinux build image files to prebuilt folder

   copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
   

   Info
   "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

   Page properties
   hidden true id Comments
   This step depends on Xilinx Device/Hardware for Zynq-7000 series copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for ZynqMP copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for ... ...

   Generate Programming Files with Vitis

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates applications design and bootable files, which are defined in "test_board\sw_lib\apps_list.csvexport files into "<project folder>\prebuilt\hardware\<short name>")
   TE::swhw_runbuild_vitisdesign -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

   Note
   TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

Launch

1. export_prebuilt

   
   

   Info
   Using Vivado GUI is the same, except file export to prebuilt folder.

   
   

2. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the "<plnx-proj-root>/images/linux" directory

3. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
   

4. Copy PetaLinux build image files to prebuilt folder

   • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
     

     Info
     "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

1. • 
     

     Page properties
     hidden true id Comments

Note:

• Programming and Startup procedure

Programming

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

Select create and open delivery binary folder

QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

TE::pr_program_flash -swapp u-boot
TE::pr_program_flash -swapp hello_te0820 (optional)

1. • This step depends on Xilinx Device/Hardware for Zynq-7000 series copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for ZynqMP copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for ... ...

     
     

2. Generate Programming Files with Vitis

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
   TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

   
   

   Note
   TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

   
   

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection

   3. Select create and open delivery binary folder

      Info
      Note: Folder

SD-Boot mode

1. Copy image.ub, boot.src and Boot.bin on SD
   use files from

   1. "<project folder>\_binaries_<Article Name>

   \

   1. " with subfolder "boot_

   linux" from generated binary folder, see: Get prebuilt boot binaries
2. or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
3. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
4. Insert SD-Card in SD-Slot.

JTAG

Not used on this example.

Usage

1. 1. <app name>" for different applications will be generated

      
      

QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   Code Block
   language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
   TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_am0010 (optional)

   
   

   Note
   To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

   
   

3. Copy image.ub and boot.scr on SD or USB
   
   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
4. Set Boot Mode to QSPI-Boot and insert SD or USB.
   • Depends on Carrier, see carrier TRM.

SD-Boot mode

1. Copy image.ub, boot.src and Boot.bin on SD
   
   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this example.

Usage

1. Prepare HW like described on section AM0010 Xilinx Reference Design
2. Connect UART USB (most cases same as JTAG)

3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

   Info
   Note: See TRM of the Carrier, which is used.

   
   

   Tip

   Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr

   
   

4. Power On PCB

   Expand
   title boot process
   1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux

5. Prepare HW like described on section AM0010 Xilinx Reference Design
6. Connect UART USB (most cases same as JTAG)

7. Select SD Card as Boot Mode (or QSPI - depending on step 1)

   Info
   Note: See TRM of the Carrier, which is used.

   Tip

   Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr

   Power On PCB

   Expand
   title boot process
   1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

   Page properties
   hidden true id Comments
   This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

   
   

   Page properties
   hidden true id Comments
   This step depends on Xilinx Device/Hardware for Zynq-7000 series for ZynqMP??? 1. ZynqMP Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for MicroblazeZynqMP??? 1.  FPGA Loads Bitfile from FlashZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. MCS Firmware configure SI5338 and starts Microblaze,FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for Microblaze 1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR for native FPGA ...

   
   

Linux

1. Open Serial Console (e.g. putty)
   
   • Speed: 115200

   • select COM Port

     Info
     Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

     
     

2. Linux Console:
   

   Code Block
   language bash theme Midnight
   petalinux login: root Password: root

   
   

   Info
   Note: Wait until Linux boot finished

   
   

3. You can use Linux shell now.
   

   Code Block
   language bash theme Midnight
   i2cdetect -y -r 0 (check I2C 0 Bus) i2cdetect -y -r 1 (check I2C 1 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check)

   
   

4. Option Features

   • Webserver to get access to Zynq
     • insert IP on web browser to start web interface
   • init.sh scripts
     • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
       

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

• Control:
• Monitoring:

Scroll Title
anchor Figure_VHM title-alignment center title Vivado Hardware Manager
Image Added

System Design - Vivado

Block Design

PS Interfaces

Activated interfaces:

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG_VOLTAGE 3.3.UNUSEDPIN PULLNONE [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific Design specific constrain

set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]

Software Design - Vitis

#############################################
#CLOCKs
#############################################
#   Y6       B224_CLK0_P
#   Y5       B224_CLK0_N                                                  
#   V6       B224_CLK1_P
#   V5       B224_CLK1_N                                                    
#set_property -dict { IOSTANDARD LVDS_25 PACKAGE_PIN Y6 } [get_ports {CLK_IN_D_224_clk_p[0]}]
#set_property -dict { IOSTANDARD LVDS_25 PACKAGE_PIN V6 } [get_ports {CLK_IN_D_224_clk_p[1]}]
#   AA13     B24_L7_P
#   AB13     B24_L7_N
#   AC14     B24_L6_P
#   AC13     B24_L6_N
set_property -dict { IOSTANDARD LVDS_25 PACKAGE_PIN AA13 } [get_ports {CLK_IN_D_24_clk_p[0]}]
set_property -dict { IOSTANDARD LVDS_25 PACKAGE_PIN AC14 } [get_ports {CLK_IN_D_24_clk_p[1]}]

##############################################
#LED and DIP Switch 
##############################################
#   D15      USER_LED[0]
#   D14      USER_LED[1]
#   G15      USER_LED[2]
#   G14      USER_LED[3]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN D15 } [get_ports {LED[0]}]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN D14 } [get_ports {LED[1]}]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN G15 } [get_ports {LED[2]}]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN G14 } [get_ports {LED[3]}]
#   F13      USER_SW[0]
#   G13      USER_SW[1]
#   E15      USER_SW[2]
#   F15      USER_SW[3]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN F13 } [get_ports {SW[0]}]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN G13 } [get_ports {SW[1]}]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN E15 } [get_ports {SW[2]}]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN F15 } [get_ports {SW[3]}]
##############################################
#HYPERRAM
##############################################
# #CK
# set_property PACKAGE_PIN AG10 [get_ports CLK_P]
# #CKN/RFU
# set_property PACKAGE_PIN AH10 [get_ports CLK_N]
# #DQ0..7
# set_property PACKAGE_PIN AB9  [get_ports {D[0]}]
# set_property PACKAGE_PIN AC11 [get_ports {D[1]}]
# set_property PACKAGE_PIN Y10  [get_ports {D[2]}]
# set_property PACKAGE_PIN AA8  [get_ports {D[3]}]
# set_property PACKAGE_PIN Y9   [get_ports {D[4]}]
# set_property PACKAGE_PIN AD11 [get_ports {D[5]}]
# set_property PACKAGE_PIN AB10 [get_ports {D[6]}]
# set_property PACKAGE_PIN AF10 [get_ports {D[7]}]
# #RWDS/RDS
# set_property PACKAGE_PIN AA10 [get_ports RWDS]
# #CSN
# set_property PACKAGE_PIN AD10 [get_ports CS0_N ]
# #RFU
# set_property PACKAGE_PIN AE10 [get_ports CS1_N]
# #RESETN
# set_property PACKAGE_PIN AB11 [get_ports RESET_N]
# #INT
# set_property PACKAGE_PIN AA11 [get_ports INT_N ]

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 2020.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2020.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_am0010

Hello AM0010 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
• CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""

U-Boot

Start with petalinux-config -c u-boot

Changes:

• CONFIG_I2C_EEPROM=y
• CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
• CONFIG_SYS_I2C_EEPROM_ADDR=0x53
• CONFIG_SYS_I2C_EEPROM_BUS=0
• CONFIG_SYS_EEPROM_SIZE=256
• CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
• CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
• CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
• CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
• CONFIG_SD_BOOT=y

Change platform-top.h:

Device Tree

/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };          
};

/*------------------ QSPI -------------------- */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        //compatible = "flash name, "micron,m25p80";
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};
/*------------------ I2C --------------------- */

&i2c0 {
    //optiga: optiga@30 {
    //    #address-cells = <1>;
    //    #size-cells = <0>;
    //    compatible = "atmel,24c08";
    //    reg = <0x30>;
    //};
    eeprom: eeprom@53 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "atmel,24c08";
        reg = <0x53>;
    };
    //crypto: crypto@60 {
    //    #address-cells = <1>;
    //    #size-cells = <0>;
    //    compatible = "atmel,24c08";
    //    reg = <0x60>;
    //};
};

&i2c1 {
  extern: extern@20 {
     compatible = "atmel,24c08";
     reg = <0x20>;
  };
};

/* ------------------ GEM3 ------------------- */
 
&gem3 {
    status = "okay";
    phy-mode = "rgmii-id";
    phy-handle = <&ethernet_phy0>;
    ethernet_phy0: ethernet-phy@0x3 {
            compatible = "marvell,88e1510";
            reg = <0x3>;
            #address-cells = <0x1>;
            #size-cells = <0x1>;
    };
};

/*------------------ USB0 ---------------------*/
/*
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
     snps,dis_u2_susphy_quirk;
    snps,dis_u3_susphy_quirk;
};
*/


/* USB  */
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
     snps,dis_u2_susphy_quirk;
    snps,dis_u3_susphy_quirk;
};
     
&usb0 {
    status = "okay";
    /delete-property/ clocks;
    /delete-property/ clock-names;
    clocks = <0x3 0x20>;
    clock-names = "bus_clk";
};
  

/*------------------- SD1 ------------------*/

&sdhci1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_sdhci1_default>;
    disable-wp;
    no-1-8-v;
};
 
&pinctrl0 {
    status = "okay";
    pinctrl_sdhci1_default: sdhci1-default {
        mux {
            groups = "sdio1_0_grp";
            function = "sdio1";
        };
 
        conf {
            groups = "sdio1_0_grp";
            slew-rate = <1>;
            io-standard = <1>;
            bias-disable;
        };
    /* 
            mux-cd {
                groups = "sdio1_cd_0_grp";
                function = "sdio1_cd";
            };
     
            conf-cd {
                groups = "sdio1_cd_0_grp";
                bias-high-impedance;
                bias-pull-up;
                slew-rate = <1>;
                io-standard = <1>;
            };
     
            mux-wp {
                groups = "sdio1_wp_0_grp";
                function = "sdio1_wp";
            };
     
            conf-wp {
                groups = "sdio1_wp_0_grp";
                bias-high-impedance;
                bias-pull-up;
                slew-rate = <1>;
                io-standard = <1>;
            };
    */ 
         
    }; 
};

/*

For Vitis project creation, follow instructions from:

Vitis

Application

---------------

Template location: "<project folder>\sw_lib\sw_apps\"

...

-

-

Device Tree

-

-

For PetaLinux installation and project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• No changes.

U-Boot

Start with petalinux-config -c u-boot

Changes:

• No changes.

Change platform-top.h:

/include/ "system-conf.dtsi"
/ {
};


- SD0 eMMC ----------------*/
&sdhci0 {
    // disable-wp;
    no-1-8-v;
};



 

FSBL patch

Must be add manually, see template

Kernel

Start with petalinux-config -c kernel

Changes:

Changes:

• # CONFIG_CPU_IDLE is not set

• # CONFIG_CPU_FREQ is not set

• CONFIG_EDAC_CORTEX_ARM64=y

  No changes.

Rootfs

Start with petalinux-config -c rootfs

Changes:

• No changes.CONFIG_i2c-tools=y

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for Zynq access. Need busybox-httpd

Additional Software

No additional software is needed.

SI5338

File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"

General documentation how you work with this project will be available on Si5338

SI5345

File location "<project folder>\misc\Si5345\Si5345-*.slabtimeproj"General documentation how you work with this project will be available on Si5345

App. A: Change History and Legal Notices

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

Legal Notices