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Artix module TE0712 with A200T, from Cameralink connector on TE0701 goes cut SATA cable to SFP2SATA adapter - the baseboard where the 7045 micro-module sits has 2 SFP slots.

 

 

 

 

 

 

 

 

Step 14: Another project in Vivado, select TE0712 as board, then PCIe IP Core in IP Catalog, selecting 1 Lane.

Step 15: Open Example Project

Step 16: Fix RXP/RXN location for GTP and select the MGTCLK tile in XDC, then build bitstream, configure FPGA

Step 17: Connect the cables!

Step 18: It should work now. If only the capacitors would be correct on the SFP2SATA adapter.

Step 19: Add VIO and ILA cores on both FPGA's google a lot, use the DSO that to look at the signals.

Step 20: measure the capacitor with SMD tweazers, see numbers 96 and nF, make decision that 96nF is good enough, it must be between 75nF and 200nF

Step 21: repeat step 19

Step 22: repeat step 20, see numbers 9.6 and nF? 10nF no good! That would fail PCIe Receiver detection and explain why the links is not up

Step 23: take 4 new capacitors 0402 from SMD kit, measure them with SMD tweazers, this time reading 100 and no 10, replace the caps.

Step 24: repeat step 19

Step 25: repeat step 20, see numbers 100 and pF? not good at all! 

Step 26: repeat step 23

Step 27: type "peek 0x60000144" in on the 7045 linux prompt, get 00000020 as result

Step 28: decode it to LTSSM state: not good its Polling.Configuration, sometimes for short while also Polling Compliance Post Timeout - Timeout is never good.

Step 29: Clocking maybe? As Sata cable has only 2 pairs I do not forward slot clock from root to device, actually for initial dirty testing I routed PS FCLK0 to PCIe IP core and GTX Tranceivers. Let me check the Zynq Clock config, olllaaaa, 50MHz! Changing FCLK0 to 100Mhz, rebuild bitstream.

Step 30: type "peek 0x60000144" in on the 7045 linux prompt, get 000008B0 as result PCIe link status L0 all ready to go!

Step 31: scroll back in bootlog: "ehci-pci: EHCI PCI platform driver" wau! I did not do it.. I did not fix anything in device tree, it was pulled in from Vivado HDF file.

 

Easy uh?