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Here, TE0710 Art ix module as hardware test bench. Frequency Counter IP Core configured for 4 channels. Reference clock is from 100 MHz oscillator. Just for testing 33.3333 MHz and 800MHz signals from FPGA Clock PLL are connected to channels 0 and 1. Channels 2 and 3 are connected to I/O Oscillator IP Core. Channel 2 I/O pin is "empty" FPGA ball from DDR3 bank with 1.5V I/O Voltage. Channel 3 I/O pin is in 1.8V bank and is connected to on-board Ufl coaxial connector with PCB trace of about 12 mm length.

This the top level design.

Clock Wizard is used to configure the FPGA Clocking, I have selected 33.3333Mhz and 800MHz, please notice that "measurement" channels are configured with no BUFG.

Frequency meter IP Core configured for 4 channels.

I/O Oscillator configured for 2 channels. The default oscillator implementation uses no fabric logic only I/O Cell is used. This minimizes the impact of fabric delays and routing to the oscillation frequency.

Utilization report: Frequency counter core uses no clock buffers (assuming the reference clock has a global buffer already). Frequency counter uses 1 DSP48E per channel, and 1 DSP48 for the reference clock. All clock measurement nets are driving exactly one load, the clock input of the DSP48E primitive, there is no other connections on that net. So it is irrelevant if the net is driven by some buffer or fabric local routing, the frequency performance of the channel is the same.

Clock resource allocation, clearly visible that all BUFG that are used are for the MMCM or Vivado ICON IP Core, none of the BUFG in the design is needed for the Frequency meter IP Core.