Page History

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Type: Schematic Change

Reason: Availability for Texas Instrument DCDCs is not good Supply chain optimization.

Impact: None.

#3 Replace TPS27082LDDCR (Q1) by MP5077GG-Z

Type: Schematic Change

Reason: Supply Chain Optimizationchain optimization.

Impact: None.

#4

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Add power supervisor BD39040MUF (U25)

Type: Schematic Change

Reason: Ferrite bead are discontinuedImproved voltage rail supervision.

Impact: None.

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. More power rails are now monitored.

#5 Add protection diode D5 to U23.3 (#MR input).

Type: Schematic Change

Reason: Oscillator UpdateAvoid voltage high-signal-state at U23 manual reset pin 3 without powered supervisor.

Impact: None.

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#6 Connect power supervisor U23 to 3.3VIN power rail (was 3.3V).

Type: Schematic Change

Reason: Oscillator UpdateAvoid high-signal-state at U23 manual reset pin 3 without powered supervisor.

Impact: None.

#5 Change pull-down/floating status for U5.T16 and U5.U16 for revision indicator.

Type: Schematic Change

Reason: Revision change indicated via pins.

Impact: None.

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#7 Change voltage divider resistors (R56, R58) to set the threshold for U23.

Type: Schematic Change

Reason: Set reset threshold for U26 to 0.905 V.

Impact: None, improved . Improved reset behaviour.

#6 Changed fiducial (PM1, PM2, PM3, PM4, PM5, PM6). ??? Is that necessary ???

Type: Schematic Change

Reason: Production optimization.

Impact: None.

#6 Removed S/N. ??? Is that necessary ???

Type: Schematic Change

Reason: Production optimization.

Impact: None.

#7 Added power supervisor BD39040MUF (U25)

Type: Schematic Change

Reason: Improved voltage rail supervision.

Impact: None. All power rails are now monitored.

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#8 Change net name "PG_DDR_PWR" to "PG_All" and connect BD39040MUF "PG_All" - signal U25.15 to system controller U26.27 with pull-up resistor R67.

Type: Schematic Change

Reason: Power Supervisor supervisor connection.

Impact: None. If custom CPLD design used, check for compatibility.

#9 Connect MIO8-Signal "SPE_SCK_FB/VCFG1" (U5.E18) to system controller (U26.8).

Type: Schematic Change

Reason: Enable boundary scan for MIO bank 1.

Impact: None. If custom CPLD design used, check for compatibility.

#10 Connect net "PS-POR-B" via resistor R75 net name "RST" to system controller (U26.9).

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Impact: None. If custom CPLD design used, check for compatibility.

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#11 Change pull-down/floating status for U5.T16 and U5.U16 for revision indicator.

Type: Schematic Change

Reason: Revision indicator via pins.

Impact: None.

#12 Replace BKP0603HS (L1, L2, L3, L4, L5, L6, L7, L8, L9, L11) by MPZ0603S121HT000

Type: Schematic Change

Reason: Ferrite beads are discontinued.

Impact: None.

#13 Replace fiducial (PM1, PM2, PM3, PM4, PM5, PM6).

Type: Schematic Change

Reason: Enable boundary scan for MIO bank 1Production optimization.

Impact: None. If custom CPLD design used, check for compatibility.

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#14 Remove decoupling capacitor (C9, C12, C30) for net "1.8V" at pins U5 bank 501.

Type: Schematic Change

Reason: Decoupling replacement ????improvement.

Impact: None. Designator changed.

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#15 Add decoupling capacitor (C9, C30, C50, C51, C88, C89, C108, C118) for net "1V".

Type: Schematic Change

Reason: Decoupling improvement for "1V" voltage rail.

Impact: None.

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#16 Change decoupling capacitor (C21, C144) for VCCPLL.

Type: Schematic Change

Reason: Decoupling improvement for VCCPLL.

Impact: None.

#17

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Add/

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Change decoupling capacitor (C107, C128) for VCCAUX and VCCPAUX.

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Type: Schematic Change

Reason: Decoupling improvement for VCCAUX and VCCPAUX.

Impact: None.

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#18 Add decoupling capacitor (C128) for AVDD3.

Type: Schematic Change

Reason: Decoupling improvement for AVDD3BOM Optimization.

Impact: None.

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#19 Change decoupling capacitor (C136, C142, C139, C145) for net DDR_PWR.

Type: Schematic Change

Reason: Decoupling improvement for VCCPLL.

Impact: None.

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#20 Add/

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Change decoupling capacitor (C50, C51, C86, C88, C89, C108, C118) for VCCBRAM.

Type: Schematic Change

Reason: Decoupling improvement for VCCBRAM.

Impact: None.

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#21 Add input capacitor (C153, C154) for DCDC U4.

Type: Schematic Change

Reason: ???Decoupling improvement for VDDQSNS and VDD.

Impact: None.

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#22 Change resistor (R21) physical size.

Type: Schematic Change

Reason: ???BOM Optimization.

Impact: None.

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. Physical dimension changed.

#23 Change testpoint TP14 from net "GND" to net "PG_ALL".

Type: Schematic Change

Reason: Decoupling improvement for VDDQSNS and VDDTest Automation.

Impact: None.

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#24 Add testpoint TP15 to net "PS-CLK".

Type: Schematic Change

Reason: Avoid high-signal-state at U23 manual reset pin 3 without powered supervisorTest Automation.

Impact: None.

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#25 Remove testpoint (TP16, TP17).

Type: Schematic Change

Reason: Avoid voltage high-signal-state at U23 manual reset pin 3 without powered supervisorOptimization.

Impact: None.

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#26 Change PCB layout of power supplies.

Type: PCB Change

Reason: DCDCs with new footprints needs need to be used.

Impact: None.

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#27 LIB update

Type: SCH and PCB Change

Reason: Update schematic symbols and footprints to latest version.

Impact: None.

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#28  Change PCB layout of Samtec B2B signals.

Type: PCB Change

Reason: Result of this PCN changes.

Impact: The length of the tracks has been changed. Pinout of Samtec B2B connectors is not affected. Changed trace length has to be taken into account in existing designs. The trace length for new revision are added to the 4x5 series pinout generator.  Please, check if change in trace length still matches your requirements. Adaption of carrier may be necessary.

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#29 Change schematic documentation.

Type: DOC Change

Reason: Documentation optimization.

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