Page History

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Reason: Revision indicator via pins.

Impact: None.

#12 Remove GND connection from FPGA "RSVDGND" pin (U5.G12).

Type: Schematic Change

Reason: Xilinx recommendation.

Impact: None.

#13 Replace BKP0603HS (L1, L2, L3, L4, L5, L6, L7, L8, L9, L11) by MPZ0603S121HT000

Type: Schematic Change

Reason: Ferrite beads are discontinued.

Impact: None.

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#14 Replace fiducial (PM1, PM2, PM3, PM4, PM5, PM6).

Type: Schematic Change

Reason: Production optimization.

Impact: None.

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#15 Remove decoupling capacitor (C9, C12, C30) for net "1.8V" at pins U5 bank 501.

Type: Schematic Change

Reason: Decoupling improvement.

Impact: None. Designator changed.

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#16 Add decoupling capacitor (C9, C30, C50, C51, C88, C89, C108, C118) for net "1V".

Type: Schematic Change

Reason: Decoupling improvement for "1V" voltage rail.

Impact: None.

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#17 Change decoupling capacitor (C21, C144) for VCCPLL.

Type: Schematic Change

Reason: Decoupling improvement for VCCPLL.

Impact: None.

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#18 Add/Change decoupling capacitor (C107, C128) for VCCAUX and VCCPAUX.

Type: Schematic Change

Reason: Decoupling improvement for VCCAUX and VCCPAUX.

Impact: None.

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#19 Add decoupling capacitor (C128) for AVDD3.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

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#20 Change decoupling capacitor (C136, C142, C139, C145) for net DDR_PWR.

Type: Schematic Change

Reason: Decoupling improvement for VCCPLL.

Impact: None.

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#21 Add/Change decoupling capacitor (C50, C51, C86, C88, C89, C108, C118) for VCCBRAM.

Type: Schematic Change

Reason: Decoupling improvement for VCCBRAM.

Impact: None.

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#22 Add input capacitor (C153, C154) for DCDC U4.

Type: Schematic Change

Reason: Decoupling improvement for VDDQSNS and VDD.

Impact: None.

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#23 Change resistor (R21) physical size.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None. Physical dimension changed.

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#24 Change testpoint TP14 from net "GND" to net "PG_ALL".

Type: Schematic Change

Reason: Test Automation.

Impact: None.

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#25 Add testpoint TP15 to net "PS-CLK".

Type: Schematic Change

Reason: Test Automation.

Impact: None.

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#26 Remove testpoint (TP16, TP17).

Type: Schematic Change

Reason: Optimization.

Impact: None.

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#27 Change PCB layout of power supplies.

Type: PCB Change

Reason: DCDCs with new footprints need to be used.

Impact: None.

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#28 LIB update

Type: SCH and PCB Change

Reason: Update schematic symbols and footprints to latest version.

Impact: None.

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#29  Change PCB layout of Samtec B2B signals.

Type: PCB Change

Reason: Result of this PCN changes.

Impact: The length of the tracks has been changed. Pinout of Samtec B2B connectors is not affected. Changed trace length has to be taken into account in existing designs. The trace length for new revision are added to the 4x5 series pinout generator.  Please, check if change in trace length still matches your requirements. Adaption of carrier may be necessary.

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#30 Change schematic documentation.

Type: DOC Change

Reason: Documentation optimization.

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