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Template Revision 2.1

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

  • Change List 2.0 to 2.1
    • Fix problem with pdf export and side scroll bar
  • Change List 1.9.1 to 2.0
    • add fix table of content
    • add table size as macro
    • removed page initial creator

Overview

Firmware for PCB CPLD with designator U5: LCMX02-1200HC

Feature Summary

  • Module Power sequencing
  • LED Status
  • FPGA IO User access

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinBank PowerDescription
Buttonin77LVCMOS33Button S2 active low
LED1out76LVCMOS33green LED D1
LTM1_ALERTin65LVCMOS33Control Interface to DC-DC converters U3 and U4 / currently_not_used
LTM2_ALERTin64LVCMOS33Control Interface to DC-DC converters U3 and U4 / currently_not_used
LTM_SCLout67LVCMOS33Control Interface to DC-DC converters U3 and U4 - DC DC regulator LTM4676 I2C
LTM_SDAinout66LVCMOS33Control Interface to DC-DC converters U3 and U4 - DC DC regulator LTM4676 I2C
PLL_SCLout14LVCMOS18PLL SI5338 I2C Interface
PLL_SDAinout15LVCMOS18PLL SI5338 I2C Interface
DDR3_SCLout43LVCMOS33DDR3 I2C Interface
DDR3_SDAinout42LVCMOS33DDR3 I2C Interface
FMC_SCLout49LVCMOS33FMC Connector I2C Interface
FMC_SDAinout48LVCMOS33FMC Connector I2C Interface
EN_1V8out58LVCMOS33Power-on sequence and monitoring - ENABLE Power regulator EP53F8QI U20
PG_1V8in59LVCMOS33Power-on sequence and monitoring - Power Good Power regulator EP53F8QI U20
EN_1V8_FMCout60LVCMOS33Power-on sequence and monitoring - ENABLE Power regulator EN6347QI U7
PG_1V8_FMCin61LVCMOS33Power-on sequence and monitoring - Power Good Power regulator EN6347QI U7
EN_3V3out51LVCMOS33Power-on sequence and monitoring - ENABLE Power regulator EN6347QI U15
PG_3V3in57LVCMOS33Power-on sequence and monitoring - Power Good Power regulator EP53F8QI U15
FEX_0_Pin1LVCMOS18goes to LED
FEX_0_Nout2LVCMOS18FMC Power Good - FMC_PG_M2C
FEX_1_Pin3LVCMOS18Control interface to clock synthesizer U9 - LMK_SCK
FEX_1_Nin4LVCMOS18Control interface to clock synthesizer U9 - LMK_SDIO
FEX_2_Pout9LVCMOS18Control interface to clock synthesizer U9 - LMK
FEX_2_Nin10LVCMOS18Control interface to clock synthesizer U9 - LMK
FEX_3_Pin12LVCMOS18Control interface to clock synthesizer U9 - LMK_CS
FEX_3_Nin13LVCMOS18Control interface to clock synthesizer U9 - LMK_SYNC
FEX_4_Nout21LVCMOS18PCIe_RST
FEX_4_Pin20LVCMOS18Control interface to clock synthesizer U9 - LMK_RESET
FEX_5_Pout16LVCMOS18F1SENSE
FEX_5_Nin17LVCMOS18F1PWM
FEX_DIRout18LVCMOS18FMC_PRESENT
EX0_P
84LVCMOS33User I/O / currently_not_used
EX0_N
83LVCMOS33User I/O / currently_not_used
EX1_P
88LVCMOS33User I/O / currently_not_used
EX1_N
87LVCMOS33User I/O / currently_not_used
EX2_P
97LVCMOS33User I/O / currently_not_used
EX2_N
96LVCMOS33User I/O / currently_not_used
EX3_P
40LVCMOS33User I/O / currently_not_used
EX3_N
41LVCMOS33User I/O / currently_not_used
EX4_P
29LVCMOS33User I/O / currently_not_used
EX4_N
30LVCMOS33User I/O / currently_not_used
PCIe_RST_inin37LVCMOS33PCIe control line RESET
LMK_CSout53LVCMOS33Control interface to clock synthesizer U9 - FEX_3_P
LMK_SCKout74LVCMOS33Control interface to clock synthesizer U9 - FEX_1_P
LMK_SDIOinout75LVCMOS33Control interface to clock synthesizer U9 - FEX_1_N when FEX_2_N='0' else 'Z';
LMK_RESETout54LVCMOS33Control interface to clock synthesizer U9 - FEX_4_P
LMK_SYNCout52LVCMOS33Control interface to clock synthesizer U9 - FEX_3_N
LMK_STAT0inout62LVCMOS33Control interface to clock synthesizer U9 / currently_not_used
LMK_STAT1inout63LVCMOS33Control interface to clock synthesizer U9 / currently_not_used
FPGA_IIC_SCLin25LVCMOS18FPGA I2C Interface
FPGA_IIC_SDAout24LVCMOS18FPGA I2C Interface
FPGA_IIC_DIRin19LVCMOS18FPGA I2C Interface
F1PWMout98LVCMOS33Fan PWM control J4
F1SENSEin99LVCMOS33Fan PWM control J4
FMC_PG_C2Mout69LVCMOS33FMC Connector Control lines
FMC_PG_M2Cin68LVCMOS33FMC Connector Control lines
FMC_PRESENTin70LVCMOS33FMC Connector Control lines
DONEin7LVCMOS18FPGA programming control and state
PROG_Bout8LVCMOS18FPGA programming control and state
dummyout34LVCMOS33dummy pin - not connected


Functional Description

More information can be found in the TEC0330 TRM.

Power

EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously to '1' at start-up.

PG signals will not be evaluated.

Reset

PROG_B is '0' when Button S2 is pressed, otherwise '1'.

LED

LEDSTATUSConditionUser defined
LED1 D1 (Green)ONButton S2 Pressed---
LED1 D1 (Green)Blink fastButton S2 not pressed, DONE=0---
LED1 D1 (Green)FEX_0_PButton S2 not pressed, DONE=1FEX_0_P

Appx. A: Change History

Revision Changes

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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REV01REV05

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  • Initial release

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Appx. B: Legal Notices

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IN:Legal Notices
IN:Legal Notices



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