Page History
...
| SoM | Base | Vivado | Status |
|---|---|---|---|
| TE0720-02-2IF | TE0701-05 | 2014.4 | released |
| TE0715-15 | TE0701-05 | 2015.2 | planned |
Block Design
TE0720, Vivado 2014.4
TE0715, Vivado 2015.4 (TPG is removed from the design)
IP Cores used
| Vendor | License | Description | |
|---|---|---|---|
| axis_fb_conv | TE | Free | Remap axi_vdma into linux framebuffer color format for axi4s_video_out |
| video_io_to_hdmi | TE | Free | |
| axi_vdma | Xilinx | Free | |
| axi4s_video_out | Xilinx | Free | |
| VTC | Xilinx | Free | Video timing generator, with AXI Control. Can be converted to fixed timing version to save resources |
| TPG | Xilinx | Free | Test pattern generator. Optional, can be removed from design |
...
Overview
Content Tools