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SDIO MIO Settings in PS7 IP Configuration if external level shifter is used:
- speed (slew rate): fastslow
- pullup: disabled
| Note |
|---|
It is important to disable the pullupspull-ups, otherwise some SD card may exhibit systematic or random problem at initialization. |
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Example settings for SDIO MIO pins (TE0720), MIO pullups are disabled.
SDIO Peripheral Clock
This clock may as of Xilinx default sometimes be set to 125MHz, this would cause Xilinx FSBL to fail on clock lookup when setting SD clock to 400KHz. SDIO peripheral clock should be set to 100MHz or 50MHz.
Level shifter
Modules that expose SDIO Interface on the B2B Connector from 1.8V VCCIO bank need SD Level shifter IC on the baseboard.
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