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The IBERT core can be defined and generated using the Vivado built-in IP Cores. And with the generated example designs the IBERT Test can be implemented.
| GT Ref Clock LocationSelection | GT Clock(MHz) | Notes | |||
|---|---|---|---|---|---|
| TE0712 | Quad_MGTREFCLK0 216 CLK0 | 125 | Si5338 Clock is connected to GT CLK2 input | ||
| TE0715 | Quad_MGTREFCLK1 112 CLK1 | 125 | Si5338 Clock is connected to GT CLK2 input | ||
| TE0741 | Quad_115 CLK1, Quad_116 CLK1 | 125 | Si5338 Clock is connected to GT CLK1 inputMGTREFCLK1 116 | 125 | Both Quads can use same refclock |
Ref clock selection to use on board fixed clock from Si5338.
Step to Step to generate the IBERT core:
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