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The IBERT core can be defined and generated using the Vivado built-in IP Cores. And with the generated example designs the IBERT Test can be implemented.

 

 GT Ref Clock LocationSelectionGT Clock(MHz)Notes
TE0712Quad_MGTREFCLK0 216 CLK0125Si5338 Clock is connected to GT CLK2 input 
TE0715Quad_MGTREFCLK1 112 CLK1125Si5338 Clock is connected to GT CLK2 input 
TE0741Quad_115 CLK1, Quad_116 CLK1125Si5338 Clock is connected to GT CLK1 inputMGTREFCLK1 116125Both Quads can use same refclock

Ref clock selection to use on board fixed clock from  Si5338.

 

Step to Step to generate the IBERT core:

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