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The customizable IBERT core for 7 series FPGA can be used for evaluating and monitoring the GTs.

The IBERT core can be defined and generated using the Vivado built-in IP Cores. And with the generated example designs the IBERT Test can be implemented.

 

 GT Clock
 GT Clock LocationGT Clock(MHz)Clock SourceNotes
TE0712Quad_216 CLK0125CLK2Si5338 Clock is connected to GT CLK2 input
TE0715Quad_112 CLK1125CLK2Si5338 Clock is connected to GT CLK2 input
TE0741Quad_115 CLK0, Quad_116 CLK0125B2B JM3 

 

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Step to Step to generate the IBERT core:

  1. Create a new IP Location.
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  2. Double-click IBERT 7 series GTP.
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  3. Define the new IBERT. Set the LineRate, select the Quad count, select the Refclk and Clock Source.
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  4. Generate the Core.
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  5.  Open the Example Design.


  6. Test

 

 

 

 

 

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References

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