Page History
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SoM | Base | Vivado | Status |
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TE0720-02-2IF | TE0701-05 | 2014.4 | released |
TE0715-15 | TE0701-05 | 2015.2 | planned |
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Block Design
IP Cores used
Vendor | License | Description | |||||
---|---|---|---|---|---|---|---|
axis_fb_conv | TE | Free | Remap axi_vdma into linux framebuffer color format for axi4s_video_out | ||||
video_io_to_hdmi | TE | Free | |||||
axi_vdma | Xilinx | Free | |||||
axi4s_video_out | Xilinx | Free | |||||
VTC | Xilinx | Free | Video timing generator, with AXI Control. Can be converted to fixed timing version to save resources | ||||
TPG | Xilinx | Free | Test pattern generator. Optional, can be removed from design |
Software support
All initialization is done in FSBL, there is no extra software or drivers needed later. Linux simple framebuffer has to be enabled in devicetree.
Note |
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FSBL has to include all initialization for the ADV7511 and IP Cores. |
Image format
This design configures the framebuffer in Linux simple framebuffer format a8r8g8b8, screen size 1280x720. Images can be converted to this format with ImageMagick.
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Overview
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