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Table of Contents

Table of Contents

Overview

The Trenz Electronic TE0725 is a low cost small-sized FPGA module integrating a Xilinx Artix-7 (15-100T) and 32 MByte Flash memory for configuration and operation.


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Refer to httpshttp://wiki.trenz-electronic.de/display/PD/TE0725+TRMorg/te0725-info for online version of this manual and the rest of available documentation of the product.

 

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Key Features

  • Xilinx Artix-7 XC7A35T (A15 to A100T) 

  • Commercial Temperature Grade (Industrial on Request)

  • 32 MByte Flash Memory

  • 2 x 50 Pin Headers with 2,54mm Pitch, Ideal for Breadboard Use

  • 87 IOs (42 + 42 + 3)
  • 100 MHz System Clock
  • I2C EEPROM

  • 3.3V Single Power Supply with On-Board Voltage Regulators

  • Size 73 x 35 mm

  • JTAG/UART Connector 

  • 2 LED's

  • Optional HyperRAM (8 to 32 MByte)
  • Optional POF Fiber Optical Adapter (125/250 Mbps)

Block Diagram

draw.io Diagram
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diagramNameTE0725-04_updated
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Main Components

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SignalPin Number
TCKJB1-4
TDOJB1-8
TDIJB1-10
TMSJB1-12
JTAGVREF(VIO)JB1-6
GNDJB1-1, JB1-2

Connector JB1 (2 x 6 pin header) is compatible with XMOD JTAG adapter TE0790. This adapter can be inserted from top onto the TE0725, if JB1 is fitted with male pin header. Optionally JB1 can be fitted with pin header from bottom, in that case the JTAG cable connector must be on the base board. When using XMOD-JTAG in JB1 then additionally USB UART is usable, and the push-button on XMOD works as configuration reset.

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ModelBitrate MB/sNotes

AFBR-59F2Z

250

On-board LED's

LEDColorFPGANotes
D2GreenM16 
D3RedDONEActive low

Connectors

All connectors are are for 100mil headers, all connector locations are in 100 mil grid. 


LEDColorFPGANotes
D2GreenM16 
D3RedDONEActive low

Power and Power-On Sequence

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Variants Currently In Production

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FPGA Chip Model

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VIN Supply Voltage [V]

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TE0725-03-35-2C

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TE0725-03-100-2C

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TE0725-03-100-2I9

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Trenz shop TE0725 overview page
English pageGerman page

Technical Specifications

Absolute Maximum Ratings

  

Parameter

MinMax

Units

Reference document

3.3V supply voltage

-0.1

3.6

V


HR I/O banks supply voltage (VCCO)-0.53.6VXilinx datasheet DS181
HR I/O banks input voltage-0.4VCCO + 0.55VXilinx datasheet DS181

Storage Temperature

-40

+85

°C


Recommended Operating Conditions

 


 
 ParameterMinMaxUnitsReference document
VIN supply voltage3.1353.45V 
HR I/O banks supply voltage (VCCO)1.143.465VXilinx datasheet DS181
HR I/O banks input voltage-0.20VCCO + 0.20VXilinx datasheet DS181
Operating Temperature0+85

°C



Note
Please check Xilinx datasheet DS181 for complete list of absolute maximum and recommended operating ratings for the Artix-7 device.

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Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.

 


All 100 mil pin headers are in 100 mil grid, the M3 mounting holes are in 50 mil grid aligned to the centers of the 100mil headers. The module is symmetrical, turning it 180 degrees will keep all I/O and Power pins in both 50 pin headers in compatible places.

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The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Weight

8.5 g Plain module.

Revision History

Hardware Revision History

 
DateRevision

Notes

PCNDocumentation Link
2016-12-0903Second production releaseClick to see PCNTE0725-03
-02First production release 
TE0725-02
-

01

Prototypes

 



Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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Document Change History 

2018-01-11Minor formatting 
 Date

Revision

ContributorsDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

Page info
infoTypeModified by
typeFlat
showVersionsfalse

  • Block Diagram is updated.

2021-09-02

v.66

John Hartfiel

  • add JTAG notes.

2021-02-11

v.65

John Hartfiel

  • Replace Links.

2017-06-07

v.60

Jan Kumann
  • Minor formatting.

2017-01-27

v.57

Jan Kumann

  • New block diagram.

2017-01-12

v.46

Jan Kumann

  • Revision 03 product images added.

2016-12-15


Thorsten Trenz

  • Hardware revision 03 specific information added.

2016-12-09

v.40

Jan Kumann

  • Hardware revision 02 block diagram added.

2016-12-02

v.1

Antti Lukats

  • Initial version.

Disclaimer

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