Page History

Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Project+Delivery+-+Xilinx+devices

Quick Start

The most Trenz Electronic FPGA Reference Designs are TCL-script based project.

There are several options to create the Vivado project from the project delivery. These options are described in Vivado Projects - TE Reference Design.

Since 2018.3 special "Module Selection Guide" is included into "_create_win_setup.cmd" and "_create_linux_setup.sh"

• Execute "_create_win_setup.cmd" or "_create_linux_setup.sh"
• Select "Module Selection Guide" (press "0" and Enter)
• Follow instructions

For manual configuration or addition command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS. If you use our prepared batch files for project creation do the following steps:

1. open "design_basic_settings.cmd/.sh" with text editor and set correct vivado path and board part number (this will be also done automatically with the "Module Selection Guide" ). How select the correct board part number is described on TE Board Part Files
2. run "vivado_create_project_guimode.cmd/.sh"

See  See Reference Design: Getting Started for more details.

If you need our Board Part files only, see Board Part Installation.

Zip Project Delivery

Zip Name Description

Last supported Release

Currently limitations of functionality

• • Important Note: QSPI Programming need special FSBL on 2017.4 or higher for all Zynq/ZynqMP. Special programming FSBL will be provided on all newer reference designs
  • Linux OS only: Vivado project generation failesfails:
    • Reason: Vivado need "en_US.UTF-8"
    • Workaround:Check language in ":$ locale" and change language in "/etc/default/locale"
  • Linux OS only: HLS generated IPs creates : [IP_Flow 19-4318 IP] ACT warning
    
    • Reason: Missing Libs
    • Workaround: Install Liberies Libraries like GCC, clib6-dev....
  • Linux OS only: VITIS software generation failed.
    • Reason: start "gmake" failed, alias is not set on Ubuntu
    • Workaround: "sudo ln -s /usr/bin/make /usr/bin/gmake" to generate alias or use  use SDK GUI to generate applications and boot files.
  • Linux OS only: Function, which used external programs.
    • Reason: Currently only set correctly for Win OS.
    • Workaround: Change TCL scripts program path manually.
  • Linux OS (Ubuntu 18.04 ) only:   Project generation fails, in case language is not englishEnglish
    
    • Workaround:Set LC_NUMERIC=en_US.UTF-8 for bash

Directory structure

Command Files

Command files will be generated with "_create_win_setup.cmd" on Windows  Windows and "_create_linux_setup.sh" on Linux OS. Linux shell files are currently not available for this release.

Windows Command Files

Linux Command Files

TE-TCL-

Extentions

Design Environment: Usage

Reference-Design: Getting Started

Reference-Design: Getting Started

• Install Xilinx Vivado Design Suite or Xilinx Vivado Webpack (free license for some Install Xilinx Vivado Design Suite or Xilinx Vivado Webpack (free license for some FPGA only: see http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html)
  (optional) Install Xilinx Vivado LabTools (Lab Edition)
• Automatically configuration of the reference-designs (only with 2018.3 scripts and newer):
  • Run "_create_win_setup.cmd" or "_create_linux_setup.sh"
    
    • select "module selection guide" and follow instructions.
      • "design_basic_settings.cmd" will be configured over this menu
• (optional for 18.3 or newer) Manual Configure the reference-design (Note: batch/bash files works only in the basefolder of the project, use _create_*_setup.cmd/sh or copy manually ):
  1. Open “design_basic_settings.cmd” with a text-editor:
      a. Set correct Xilinx Environment:
          @set XILDIR=C:/Xilinx
          @set VIVADO_VERSION=20202021.2
          Program settings will be search in :
          %XILDIR%/VIVADO/%VIVADO_VERSION%/
          %XILDIR%/Vivado_Lab/%VIVADO_VERSION%/
          %XILDIR%/Vitis/%VIVADO_VERSION%/
          Example directory: c:/Xilinx/Vivado/20202021.2/
          Attention: Scripts are supported only with predefined Vivado Version!
      b. Set the correct module part-number:
          @set PARTNUMBER=x
          You found the available Module Numbers in <design_name>"<project folder>/board_files/<board_series>_board_files.csv"
      c. Set Application name (for programming with batch-files only):
          @set SWAPP=NA
          NA (No Software Project) used *.bit or *.mcs from <design_name>"<project folder>/prebuilt/hardware/<board_file_shortname>"
         <app_name> (Software Project) used *.bit or *.mcs or *.bin from <design_name>"<project folder>/prebuilt/boot_images/<board_file_shortname>/<app_name>"
• Create all prebuilt files in one step:
  2. Run “design_run_project_batchmode.cmd”
• (optional to Step 2) Create all prebuilt files in single steps:
  3. Run “vivado_create_project_guimode.cmd”:
      A Vivado Project will be create and open  open in ./vivado
  4. Type “TE::hw_build_design” on Vivado TCL-Console:
      Run Synthesesynthesis, Implement and create Bitfile and optional MCSfile
  5. Type “TE::sw_run_vitis -all -no_gui” on Vivado TCL-Console:
      Create all Software Applications from <design_name>"<project folder>/sw_lib/apps_list.csv"
  6. (optional to Step 5) Type “TE::sw_run_vitis ” on Vivado TCL-Console:
      Create a SDK Project in <design_name>"<project folder>/workspace/sdk"
      Include Hardware-Definition-File, Bit-file and local Software-libraries from  <design_name>from "<project folder>/sw_lib/sw_apps"

• Programming FPGA or Flash Memory with prebuilt Files:
  7. Connect your Hardware-Modul with PC via JTAG.
  With Batch-file:
  8. (optional) Zynq-Devices Flash Programming (*.bin) or FPGA-Device Flash Programming (*.mcs):
      Run “program_flash.cmd”
  10. (optional) FPGA-Device Programming (*.bit):
        Run “program_fpga_bitfile.cmd”
  With Vivado/Labtools TCL-Console:
  11. Run “vivado_open_existing_project_guimode.cmd” or “labtools_open_project_guimode.cmd” to open Vivado  or or LabTools
  12. (optional) Zynq-Devices Flash Programming (*.bin):
        Type “TE::pr_program_flash -swap <app_name>” on Vivado TCL-Console
        Used .bin(Zynq)/.mcs(native FPGA)<design_name> "<project folder>/prebuilt/boot_images/<board_file_shortname>/<app_name>"
  13. (optional) FPGA-Device Programming (*.bit):
        Type “TE:: pr_program_jtag_bitfile -swap <app_name>” on Vivado TCL-Console
        Used *.bit from <design_name>"<project folder>/prebuilt/boot_images/<board_file_shortname>/<app_name>"

Basic Design Settings

Initialise TE-scripts on Vivado/LabTools

• Variant 1 (recommended):
  • Start the project with the predefined command file (vivado_open_existing_project_guimode.cmd) respectively LabTools with (labtools_open_project_guimode.cmd)
• Variant 2:
  • Create your own Initialisation Button on the Vivado GUI:
    • Tools → Customize Commands → Customize Commands...
    • Push
    • Type Name ex.: Init Scripts
    • Press Enter
    • Select Run command and insert:
      
      • for Vivado: cd [get_property DIRECTORY [current_project]]; source -notrace "../scripts/reinitialise_all.tcl"
      • for LabTool: cd [pwd]; source -notrace "../scripts/reinitialise_all.tcl"
        
    • Press Enter
    • A new Button is shown on the Vivado GuiGUI: All Scripts are reinitialised, if you press this Button.
      
• Variant 3:
  • Reinitialise Script on Vivado TCL-Console:
    • Type: source ../scripts/reinitialise_all.tcl
      

Use predefined TE-Script functions

• Variant 1 (recommended):
  • Typ Type function on Vivado TCL Console, ex.: TE::help
  • TE::help
    
    • Show all predefined TE-Script functions.
  • TE:<functionname> <function_name> -help  help
    
    • Show short description of this function.
    • Attention: If -help argument is set, all other args will be ignored. 
• Variant 2:
  • Create your own function Button on the Vivado GUI:
    • Tools → Customize Commands → Customize Commands...
    • Push +
    • Type Name ex.: Run SDK
      
    • Press Enter
      
    • Select Run command and insert function:
      • Variante 1 (no Vivado request window for args):
        • insert function and used args, ex.: TE::sw_program_zynq -swapp hello_world
      • Variant 2 (Vivado request window for args):
        • insert function, ex.:TE::sw_program_zynq
        • Press Define Args...
        • For every arg:
          
          • Push
          • Typ Type Name, Comment, Default Value and set optional
          • Press Enter
            
          • Example for args:
            • Push
            • Index, Key Name, -swapp,
            • Push
            • Appname, Arg, hello_world,
              
          •  
    • Press Enter
    • A new Button is shown on the Vivado GuiGUI.

Environment Variables

Local

Global

Hardware Design

Board Part Files

More details see TE Board Part Files

Structure Board Parts

Board Parts are located on subfolder "board_files", with the name of the special board. Revisions are splitt split in the subfolder of the board part <boardpart_name><version>

Every Version of a Board Parts consists of four files:

• board.xml
  
• part0_pins.xml
• preset.xml
• picture.jpg or picture.png

Board Part or Design Extension

Board Part Extensions are TCL-Scripts, which can be sourced in Vivado Block Design. Thy are usable with TE-Scripts only. It contains additional settings of PS-settings or special carrier-board design changes.

Use Reference Designs or Vivado TCL-Console (TE-Script extensions, see Initialise TE-scripts on Vivado/LabTools): TE::hw_blockdesign_create_bd -help to create PS with full settings. Or source the TCL file manually direct after "Run Block Automation" 

Possible:

• Board Part PS settings  are located on subfolder "board_files/preset_extension/" with file name *_preset.tcl.
• Design modiflications modifications are located on subfolder "board_files/bd_mod/" with file name *_bd.tcl.
  

Board Part CSV Description

Board Part csv file is used for TE-Scripts only.

Block Design Conventions

• Only one Block-Design per project is supported

• Recommended BD-Names (currently importend for some TE-Scripts):
   

  Name	Description
  zsys	Idendify Identify project as Zynq Project with processor system (longer name with *zsys* are supported too)
  zusys	Idendify Identify project as UltraScaleZynq Project with processor system (longer name with *zusys* are supported too)
  msys	Idendify project Identify project as Microblaze Project with processor system (longer name with *msys* are supported too)
  fsys	Idendify Identify project as FPGA-fabric Project without processor system (longer name with *fsys* are supported too)

   
  

• Create Basic Block Design with PS Board-Part Preset and Carrier-Board extended settings (only if subfolder carrier_extension with tcl files is available), use TE::hw_blockdesign_create_bd -help
  

XDC Conventions

• All *.xdc from <design_name><project folder>/constrains/ are load into the vivado project on project creation.
  Attention: If subfolder <design_name><project folder>/constrains/<board_file_shortname> is defined, it will be used the subfolder constrains only for this module!

• Recommended XDC-Names (used for Vivado XDC-options):

  Property	Name part	Description
  Set Processing Order	*_e_*	set to early
  	*_l_*	set to late
  		set to normal
  Set Used In	*_s_*	used in synthese synthesis only
  	*_i_*	used in implement only
  		used in both, synthese synthesis and implement

  
  

Backup Block Design as TCL-File

• Backup your Block-Design with TCL-Command "TE::hw_blockdesign_export_tcl" in <design_name><project folder>/block_design/
  It will be saved as *_bd.tcl
  Attention: If subfolder <design_name><project folder>/block_design/<board_file_shortname> or  <design_name><project folder>/block_design/PCB Revision> is defined, it will be saved there!
                                 Only one *.tcl file shoud should be in the backup folder respectively the subfolder <board_file_shortname>

Microblaze

Firmware

• Microblaze Firmware (*.elf) can be add to the source folder <design_name><project folder>/firmware/<Microblaze IP Instance>.
• For MCS-Core use MCS IP Instance Name. This name must use *mcs* or *syscontrol* in the name.

Software Design

Vitis: Generate predefined software from libraries

• To generate predefined software from libraries, run "TE::sw_run_vitis -all -no_gui" on Vivado TCL-Console
• All programs in in <design_name><project folder>/sw_lib/apps_list.csv are generated automaticity
• Supported are local application libaries from <design_name>libraries from <project folder>/sw_lib/sw_apps or the most Xilinx SDK Applications found in %XILDIR%/SDK/%VIVADO_VERSION%/data/embeddedsw/lib/sw_app

VITIS: Create user software project

• To start SDK project, run "TE::sw_run_vitis" on Vivado TCL-Console or run "TE::sw_run_vitis -workspace_only" on Vivado TCL-Console
  Include Hardware-Definition-File (XSA), Bit-file and local Software-libraries from  <design_name>from "<project folder>/sw_lib/sw_apps"
• To use Hardware-Definition-File, Bit-file from prebuilt folder without building the vivado hardware project, run "sdk_create_prebuilt_project_guimode.cmd" or type  type "TE::sw_run_vitis -prebuilt_xsa <board_number>" on Vivado-TCL-Console
  
• To open an existing SDK-project without update HDF-Data, type  type "TE::sw_run_vitis -gui_only" on Vivado-TCL-Console

Advanced Usage

Attention not all features of the TE-Scripts are supported in the advanced usage!

User defined board part csv file

To modifiy modify current board part csv list, make a copy of the original csv and rename with suffix "_mod.csv", ex.TE0782_board_files.csv as TE0782_board_files_mod.csv. Scripts used modified csv instead of the original file.

See Chapter Board Part Files for more information.

User defined Settings

• Vivado settings:
  • Vivado Project settings (corresponding TCL-Commands) can be saved as a user defined file "<design_name><project folder>/settings/project_settings.tcl". This file will be loaded automatically on project creation.
    
• Script settings:
  • Additional script settings (only some predefined  predefined variables) can be  saved as a user defined file "<design_name><project folder>/settings/development_settings.tcl". This file will be loaded automatically on script initialisation.
• Design settings:
  • Additional script settings (only some predefined  predefined variables) can be  saved as a user defined file "<design_name><project folder>/settings/design_settings.tcl". This file will be loaded automatically on script initialisation.
• ZIP ignore list:
  • Files which should not be added in the backup file can be can be defined in this file: "<design_name><project folder>/settings/zip_ignore_list.tcl". This file will be loaded automaticaly automatically on script initialisation.
• SDSOC settings:
  • SDSOC settings will are deposited on the following folder: "<design_name><project folder>/settings/sdsoc"

User defined TCL Script

TCL Files from "<design_name><project folder>/settings/usr" will be load automaticaly automatically on script initialisation.

SDSOC-Template

SDSOC description and files to generate SDSoC project are deposited on the following folder: "<design_name><project folder>/settings/sdsoc"

HDL-Design

HDL files can be saved in the subfolder "<design_name><project folder>/hdl/" as single files or <design_name><project folder>/hdl/folder/ and all subfolders or "<design_name><project folder>/hdl/<shortname>" and all subfolders of "<design_name><project folder>/hdl/<shortname>". They will be loaded automatically on project creation. Available formats are *.vhd, *.v and *.sv.   A own top-file must be specified with the name "<design<project folder>_name>_top.v" or "<design_name><project folder>_top.vhd".

To set file attributes, the file name must include "_simonly_" for simulation only and "_synonly_" for synthese synthesis only.

IP-cores (*.xci). can be saved in the subfolder "<design_name><project folder>/hdl/xci" or "<design_name><project folder>/hdl/xci/<shortname>". They will be loaded automatically on project creation.

IP -TCL desciption description (*_preset.tcl). can be saved in the subfolder "<design_name><project folder>/hdl/tcl" or "<design_name><project folder>/hdl/tcl/<shortname>". They will be loaded automatically on project creation.

• *_preset.tcl must include
  • TCL part for IP creation: create_ip -name ...
    
  • TCL part for IP configuration: set_property -dict...
  • TCL part for IP target generation: generate_target {instantiation_template} .....
    

Checklist / Troubleshoot

1. Are you using exactly the same Vivado version? If not then the scripts will not work, no need to try.
2. Ary Are you using Vivado in Windows PC? Vivado works in Linux also, but the scripts are tested on Windows only.
3. Is you PC OS Installation English? Vivado may work on national versions also, but there have been known problems.
4. Win OS only: Use short path name, OS allows only 256 characters in normal path.
5. Linux OS only: Use bash as shell and add access rights to bash files. Check with "ls ls /bin/sh". It should be desplaydisplay: /bin/sh -> bash. Access rights can be changed with "chmod"
6. Are space character on the project path? Somtimes Sometimes TCL-Scripts can't handle this correctly. Remove spaces from project path.
7. Did you have the newest reference design build version? Maybe it's only a bug from a older version.
8. Check <design_name><project folder>/v_log/vivado.log? If no logfile exist, wrong xilinx paths are set in design_basic_settings.cmd
9. On project creation process old files will be deleted. Sometimes the access will be denied by os (synchronisiation synchronisation problem) and the scripts canceledcancelled. Please try again. 
   
10. If nothing helps, send a mail to Trenz Electronic Support (support[at]trenz-electronic.de) with subject line "[TE-Reference Designs] ",   the complete zip-name from your reference design and the last log file (<design_name><project folder>/v_log/vivado.log)

References

1. Vivado
2. Vivado Design Suite User Guide - Getting Started  (UG910)
3. Vivado Design Suite User Guide - Getting Started (UG910)
4. Vivado Design Suite User Guide - Using the Vivado IDE (UG893)
5. Vivado Design Suite User Guide - I/O and Clock Planning (UG899)
6. Vivado Design Suite User Guide - Programming and Debugging (UG908)
7. Zynq-7000 All Programmable SoC Software Developers Guide (UG821)
8. SDSoC Environment User Guide - Getting Started (UG1028)
9. SDSoC Environment -   User Guide (UG1027)
10. SDSoC Environment User Guide - Platforms and Libraries (UG1146)

Document Change History

To get content of older revision  revision got to "Change History"   of this page and select older revision number.

<!--
Generate new entry:
1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview, Vivado Version(or update)to the empty row
3.Update Metadate =Page Information Macro Preview+1
  -->