Page History
Table of contents
Table of Contents |
---|
Zip Project Delivery
Zip Name Description
Description | PCB Name | Project Name+(opt. Variant) | supported VIVADO Version | Build Version and Date | ||||
---|---|---|---|---|---|---|---|---|
Example: | TE0726 | - | test_board_noprebuilt | - | vivado_2015.4 | - | build_26_20160415133543 | .zip |
Last supported Release
Type or File | Version |
---|---|
Vivado Design Suite | 2015.4 |
Trenz Project Scripts | 2015.4.32 |
Trenz <board_series>_board_files.csv | 1.2 |
Trenz apps_list.csv | 1.7 |
Trenz zip_ignore_list.csv | 1.0 |
Directory structure
File or Directory | Type | Description |
---|---|---|
<design_name> | base directory | Base directory with predefined batch files (*.cmd) to generate or open VIVADO-Project |
<design_name>/block_design/ | source | Script to generate Block Design in Vivado (*_bd.tcl). (optional) Some board part designs used subfolder <board_file_shortname> with Board Part specific Block Design (*_bd.tcl). |
<design_name>/board_files/ | source | Local board part files repository and a list of available board part files (<board_series>_board_files.csv) |
<design_name>/constraints/ | source | Project constrains (*.xdc). Some board part designs used subfolder <board_file_shortname> with additional constrains (*.xdc) |
<design_name>/doc/ | source | Documentation |
<design_name>/ip_lib/ | source | Local Vivado IP repository |
<design_name>/misc/ | source | (Optional) Directory with additional sources |
<design_name>/prebuilt/boot_images/ | prebuilt | Directory with prebuilt boot images (*.bin) and configuration files (*.bif) for zynq and configured hardware files (*.bit and *.mcs) for micoblaze included in sub-folders: default or <board_file_shortname>/<app_name> |
<design_name>/prebuilt/hardware/ | prebuilt | Directory with prebuilt hardware sources (*.bit, *hdf, *.mcs) and reports included in subfolders: default or <board_file_shortname> |
<design_name>/prebuilt/software/ | prebuilt | (Optional) Directory with prebuilt software sources (*.elf) included in subfolders: default or <board_file_shortname>/<app_name> |
<design_name>/prebuilt/os/ | prebuilt | (Optional) Directory with predefined OS images included in subfolders <os_name>/<board_file_shortname> or <os_name>/default |
<design_name>/scripts/ | source | TCL scripts to build a project |
<design_name>/settings/ | source | (Optional) Additional design settings: zip_ignore_list.csv, vivado project settings, SDSOC settings |
<design_name>/software/ | source | (Optional) Directory with additional software |
<design_name>/os/ | source | (Optional) Directory with additional os sources in in subfolders <os_name> |
<design_name>/sw_lib/ | source | (Optional) Directory with local SDK/HSI software IP repository and a list of available software (apps_list.csv) |
<design_name>/v_log/ | generated | (Temporary) Directory with vivado log files (used only when Vivado is started with predefined command files (*.cmd) from base folder otherwise this logs will be writen into the vivado working directory) |
<design_name>/vivado/ | work, generated | (Temporary) Working directory where Vivado project is created. Vivado project file is <design_name>.xpr |
<design_name>/vivado_lab/ | work, generated | (Optional/Temporary) Working directory where Vivado LabTools is created. LabTools project file is <design_name>.lpr |
<design_name>/workspace/hsi | work, generated | (Optional/Temporary) Directory where hsi project is created |
<design_name>/workspace/sdk | work, generated | (Optional) Directory where sdk project is created |
<design_name>/sdsoc | work, generated | (Optional) Directory where SDSOC project is created |
<design_name>/backup/ | generated | (Optional) Directory for project backups |
Windows Command Files
File Name | Description |
---|---|
Design + Settings | |
design_basic_settings.cmd | Settings for the other *.cmd files. Following Settings are avaliable:
|
design_clear_design_folders.cmd | (optional) Attention: Delete "<design_name>/v_log/", "<design_name>/vivado/", "<design_name>/vivado_lab/", "<design_name>/sdsoc/", and "<design_name>/workspace/" directory with related documents! |
design_run_project_batchmode.cmd | (optional) Create Project with setting from "design_basic_settings.cmd" and source folders. Build all Vivado hardware and software files if the sources are available. Delete "<design_name>/vivado/", and "<design_name>/workspace/hsi/" directory with related documents before Projekt will created. |
Hardware Design | |
vivado_create_project_guimode.cmd | Create Project with setting from "design_basic_settings.cmd" and source folders. Vivado GUI will be opened during the process. Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Projekt will created. |
vivado_create_project_batchmode.cmd | (optional) Create Project with setting from "design_basic_settings.cmd" and source folders. Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Projekt will created. |
vivado_open_existing_project_guimode.cmd | Opens an existing Project "<design_name>/vivado/<design_name>.xpr" and restore Script-Variables. |
Software Design | |
sdk_create_prebuilt_project_guimode.cmd | (optional) Create SDK project with hardware definition file from prebuild folder. It used the *.hdf from: <design_name>/prebuilt/hardware/<board_file_shortname>/. Set <board_file_shortname> and <app_name> in "design_basic_settings.cmd". |
Programming | |
program_flash_binfile.cmd | (optional) For Zynq Systems only. Programming Flash Memory via JTAG with specified Boot.bin. Used SDK Programmer (Same as SDK "Program Flash") or LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the boot.bin from: <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>. Settings are done in "design_basic_settings.cmd". |
program_flash_mcsfile.cmd | (optional) For Non-Zynq Systems only. Programming Flash Memory via JTAG with specified <design_name>.mcs. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.mcs from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd". |
program_fpga_bitfile.cmd | (optional) Programming FPGA via JTAG with specified <design_name>.bit. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.bit from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd". |
labtools_open_project_guimode.cmd | (optional) Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd". |
TE-TCL-Extentsions
...
Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_hdf <arg> isn't set.
Copy the Hardware Defintition file to the working directory:<design_name>/workspace/hsi
Run HSI in <design_name>/workspace/hsi for all Programes listed in <design_name>/sw_lib/apps_list.csv
If HSI is finished, BIF-GEN and BIN-Gen are running for these Apps in the prepuilt folders <design_name>/prebuilt/...
You can deactivate different steps with following args :
- -no_hsi : *.elf filesgeneration is disabled
- -no_bif : *.bif files generation is disabled
- -no_bin : *.bin files generation is disabled
- -no_bitmcs: *.bit and *.mcs file (with software design) is disabled
...
Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_hdf <arg> isn't set.
Copy the Hardware Defintition file to the working directory:<design_name>/workspace/sdk
Start SDK GUI in this workspace
...
Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -used_board <arg> isn't set (Vivado only).
Programming Bitfile from <design_name>/prebuilt/hardware/<board_file_shortname> to the fpga device.
If "-used_basefolder_bitfile" is set, the Bitfile (*.bit) from the base folder (<design_name>) is used instead of the prebuilts. Attention: Take only one Bitfile in the basefolder!
...
...
...
...
...
...
(MicroBlaze only) If "-swapp" is set, the MCSfile with *.elf configuration is used from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
...
Make a Backup from your Project in <design_name>/backup/
Zip-Program Variable must be set in start_settings.cmd. Currently only 7-Zip is supported.
...
Create SDSOC-Workspace. Currently only on some Reference-Designs available. Run [-check_only] option to check SDSOC ready state.
...
Design Environment: Usage
Reference-Design: Getting Started
...
...
Basic Design Settings
Project Configuration
- Unzip project files
- Rename basefolder (basefolder name is used as project name)
- Edit design_basic_settings.cmd
- Select the correct Xilinx Program path (See: Windows Command Files → design_basic_settings.cmd)
- Select the correct board part number for your PCB (See: Windows Command Files → design_basic_settings.cmd)
- Other settings are optional (See: Windows Command Files → design_basic_settings.cmd)
- Excecute vivado_create_project_guimode.cmd or vivado_create_project_batchmode.cmd to generate a vivado project with the predefined Block Design from the Block Design folder
- Open Vivado with vivado_open_existing_project_guimode.cmd (if you use vivado_create_project_guimode.cmd on step 4, you didn't need this)
- Open the Block Design and create your own design inside this Block Design.
- Backup your Block Design as tcl-script: Type "TE::hw_blockdesign_export_tcl" on Vivado Tcl Console. The old one will be overwritten.
- Build your Design...
Initialise TE-scripts on Vivado/LabTools
- Variant 1 (recommended):
- Start the project with the predefined command file (vivado_open_existing_project_guimode.cmd) respectively LabTools with (labtools_open_project_guimode.cmd)
- Variant 2:
- Create your own Initialisation Button on the Vivado GUI:
- Tools → Customize Commands → Customize Commands...
- Push
- Type Name ex.: Init Scripts
- Press Enter
- Select Run command and insert:
- for Vivado: cd [get_property DIRECTORY [current_project]]; source -notrace "../scripts/reinitialise_all.tcl"
- for LabTool: cd [pwd]; source -notrace "../scripts/reinitialise_all.tcl"
- Press Enter
- A new Button is shown on the Vivado Gui: All Scripts are reinitialised, if you press this Button.
- Create your own Initialisation Button on the Vivado GUI:
- Variant 3:
- Reinitialise Script on Vivado TCL-Console:
- Type: source ../scripts/reinitialise_all.tcl
- Type: source ../scripts/reinitialise_all.tcl
- Reinitialise Script on Vivado TCL-Console:
Use predefined TE-Script functions
- Variant 1 (recommended):
- Typ function on Vivado TCL Console, ex.: TE::help
- TE::help
- Show all predefined TE-Script functions.
- TE:<functionname> -help
- Show short description of this function.
- Attention: If -help argument is set, all other args will be ignored.
- Variant 2:
- Create your own function Button on the Vivado GUI:
- Tools → Customize Commands → Customize Commands...
- Push +
- Type Name ex.: Run SDK
- Press Enter
- Select Run command and insert function:
- Variante 1 (no Vivado request window for args):
- insert function and used args, ex.: TE::sw_program_zynq -swapp hello_world
- Variant 2 (Vivado request window for args):
- insert function, ex.:TE::sw_program_zynq
- Press Define Args...
- For every arg:
- Push
- Typ Name, Comment, Default Value and set optional
- Press Enter
- Example for args:
- Push
- Index, Key Name, -swapp,
- Push
- Appname, Arg, hello_world,
- Variante 1 (no Vivado request window for args):
- Press Enter
- A new Button is shown on the Vivado Gui.
- Create your own function Button on the Vivado GUI:
Hardware Design
Block Design Conventions
- Only one Block-Design per project is supported
Recommended BD-Names (currently importend for some TE-Scripts):
Name Description zsys Idendify project as Zynq Project with processor system (longer name with *zsys* are supported too) zusys Idendify project as UltraScaleZynq Project with processor system (longer name with *zusys* are supported too) msys Idendify project as Microblaze Project with processor system (longer name with *msys* are supported too) fsys Idendify project as FPGA-fabric Project without processor system (longer name with *fsys* are supported too)
XDC Conventions
- All *.xdc from <design_name>/constrains/ are load into the vivado project on project creation.
Attention: If subfolder <design_name>/constrains/<board_file_shortname> is defined, it will be used the subfolder constrains only for this module! Recommended XDC-Names (used for Vivado XDC-options):
Property Name part Description Set Processing Order *_e_* set to early *_l_* set to late set to normal Set Used In *_s_* used in synthese only *_i_* used in implement only used in both, synthese and implement
Backup Block Design as TCL-File
- Backup your Block-Design with TCL-Command "TE::hw_blockdesign_export_tcl" in <design_name>/block_design/
It will be saved as *_bd.tcl
Attention: If subfolder <design_name>/block_design/<board_file_shortname> is defined, it will be saved there!
Only one *.tcl file shoud be in the backup folder respectively the subfolder <board_file_shortname>
Software Design
HSI: Generate predefined software from libraries
- To generate predefinde software from libraries, run "TE::sw_run_hsi" on Vivado TCL-Console
- All programs in in <design_name>/sw_lib/apps_list.csv are generated automaticly
- Supported are local application libaries from <design_name>/sw_lib/sw_apps or the most Xilinx SDK Applications found in %XILDIR%/SDK/%VIVADO_VERSION%/data/embeddedsw/lib/sw_app
SDK: Create user software project
...
Checklist / Troubleshoot
- Are you using exactly the same Vivado version? If not then the scripts will not work, no need to try.
- Ary you using Vivado in Windows PC? Vivado works in Linux also, but the scripts are tested on Windows only.
- Is you PC OS Installation English? Vivado may work on national versions also, but there have been known problems.
- Are space character on the project path? Somtimes TCL-Scripts can't handle this correctly. Remove spaces from project path.
- Did you have the newest reference design build version? Maybe it's only a bug from a older version.
- Check <design_name>/v_log/vivado.log? If no logfile exist, wrong xilinx paths are set in design_basic_settings.cmd
- If nothing helps, send a mail to trenz support (support(at)trenz-electronic.de) with subject line "[TE-Reference Designs] ", the complete zip-name from your reference design and the last log file (<design_name>/v_log/vivado.log)
References
...