Page History

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Description	PCB Name		Project Name+(opt. Variant)		supported VIVADO Version		Build Version and Date
Example:	te0715	-	-test_board(_noprebuilt)	-	vivado_20172018.42	-	build_01_20180105195436	.zip

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Type or File	Version
Vivado Design Suite	20172018.42
Trenz Project Scripts	20172018.42.1002
Trenz <board_series>_board_files.csv	1.3
Trenz apps_list.csv	2.01
Trenz zip_ignore_list.csv	1.0
Trenz mod_bd.csv (not included)	1.1

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- Important Note: QSPI Programming need special FSBL on 20172018.4 2 for all Zynq/ZynqMP. Special programming FSBL will be provided on 20172018.4 2 reference designs
- Linux OS only: HSI software generation failed.
  - Reason: start "gmake" failed, alias is not set on Ubuntu
  - Workaround: "sudo ln -s /usr/bin/make /usr/bin/gmake" to generate alias or use SDK GUI to generate applications and boot files.
- Linux OS only: Function, which used external programs.
  - Reason: Currently only set correctly for Win OS.
  - Workaround: Change TCL scripts program path manually.

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File or Directory	Type	Description
<design_name>	base directory	Base directory with predefined batch files (*.cmd) to generate or open VIVADO-Project
<design_name>/block_design/	source	Script to generate Block Design in Vivado (_bd.tcl). (optional) Some board part designs used subfolder <board_file_shortname> with Board Part specific Block Design (_bd.tcl).
<design_name>/board_files/	source	Local board part files repository and a list of available board part files (<board_series>_board_files.csv)
<design_name>/board_files/carrier_extension	source	(Optional) Additional TCL-Scripts to extend Board Part PS-Preset with carrier board specific settings.
<design_name>/console	source	folder with different console command files. Use _create_win_setup.cmd or _create_linux_setup.sh to generate files on top folder.
<design_name>/constraints/	source	Project constrains (.xdc). Some board part designs used subfolder <board_file_shortname> with additional constrains (.xdc)
<design_name>/doc/	source	Documentation
<design_name>/hdl/	source	HDL-File and XCI-Files. Advanced usage only!
<design_name>/firmware/	source	ELF-File Location for MicroBlaze Firmware. Additional sub folder is used for MicroBlaze identification (sub folder path must be the same like bd hierachie).
<design_name>/ip_lib/	source	Local Vivado IP repository
<design_name>/misc/	source	(Optional) Directory with additional sources
<design_name>/prebuilt/	prebuilt	Contains a readme with location information of different assembly variants
<design_name>/prebuilt/boot_images/	prebuilt	Directory with prebuilt boot images (.bin) and configuration files (.bif) for zynq and configured hardware files (.bit and .mcs) for micoblaze included in sub-folders: default or <board_file_shortname>/<app_name>
<design_name>/prebuilt/hardware/	prebuilt	Directory with prebuilt hardware sources (.bit, hdf, *.mcs) and reports included in subfolders: default or <board_file_shortname>
<design_name>/prebuilt/software/	prebuilt	(Optional) Directory with prebuilt software sources (*.elf) included in subfolders: default or <board_file_shortname>/<app_name>
<design_name>/prebuilt/os/	prebuilt	(Optional) Directory with predefined OS images included in subfolders <os_name>/<board_file_shortname> or <os_name>/default
<design_name>/scripts/	source	TCL scripts to build a project
<design_name>/settings/	source	(Optional) Additional design settings: zip_ignore_list.csv, vivado project settings, SDSOC settings
<design_name>/software/	source	(Optional) Directory with additional software
<design_name>/os/	source	(Optional) Directory with additional os sources in in subfolders <os_name>
<design_name>/sw_lib/	source	(Optional) Directory with local SDK/HSI software IP repository and a list of available software (apps_list.csv)
<design_name>/v_log/	generated	(Temporary) Directory with vivado log files (used only when Vivado is started with predefined command files (*.cmd) from base folder otherwise this logs will be writen into the vivado working directory)
<design_name>/vivado/	work, generated	(Temporary) Working directory where Vivado project is created. Vivado project file is <design_name>.xpr
<design_name>/vivado_lab/	work, generated	(Optional/Temporary) Working directory where Vivado LabTools is created. LabTools project file is <design_name>.lpr
<design_name>/workspace/hsi	work, generated	(Optional/Temporary) Directory where hsi project is created
<design_name>/workspace/sdk	work, generated	(Optional) Directory where sdk project is created
<design_name>/.../SDSoC_PFM	work, generated	(Optional) Directory where SDSOC project is created
<design_name>/.../export	work, generated	(Optional) Directory for internal usage
<design_name>/backup/	generated	(Optional) Directory for project backups

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File Name	Description
Design + Settings
_use_virtual_drive.cmd	(Option) Create virtual drive for project execution. See Xilinx AR#52787
design_basic_settings.cmd	Settings for the other .cmd files. Following Settings are avaliable: General Settings: (optional) DO_NOT_CLOSE_SHELL: Shell do not closed after processing (optional) ZIP_PATH: Set Path to installed Zip-Program. Currently 7-Zip are supported. IUsed for predefined TCL-function to Backup project. (optional) ENABLE_SDSOC: Enable SDSOC Setting. Currently only for some reference project as beta version! Xilinx Setting: XILDIR: Set Xilinx installation path (Default: c:\Xilinx). VIVADO_VERSION: Current Vivado/LabTool/SDK Version (Example:20172018.42). Don't change Vivado Version. Xilinx Software will be searched in: VIVADO (optional for project creation and programming): %XILDIR%\Vivado\%VIVADO_VERSION%\ and for SDSoC on %XILDIR%\SDx\%VIVADO_VERSION%\Vivado\ SDK (optional for software projects and programming): %XILDIR%\SDK\%VIVADO_VERSION%\ LabTools (optional for programming only): %XILDIR%\Vivado_Lab\%VIVADO_VERSION%\ SDSOC (optional): %XILDIR%\SDx\%VIVADO_VERSION%\ Board Setting: PARTNUMBER: Set Board part number of the project which should be created Available Numbers: (you can use ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list) Used for project creation and programming To create empty project without board part, used PARTNUMBER=-1 (use GUI to create your project. No block design tcl-file should be in /block_design) Example TE0726 Module : USE ID \|USE PRODID PARTNUMBER=1 \|PARTNUMBER=te0726-01 Programming Settings(programfile.cmd): SWAPP: Select Software App, which should be configured. Use the folder name of the <design_name>/prebuilt/boot_image/<partname>/* subfolder. The bin,.mcs or .bit from this folder will be used. If you will configure the raw .bit or .mcs .bin from the <design_name>/prebuilt/hardware/<partname>/ folder, use @set SWAPP=NA or @set SWAPP="". Example: SWAPP=hello_world → used the file from prebuilt/boot_image/<partname>/hello_world SWAPP=NA → used the file from <design_name>/prebuilt/boot_image/<partname>/ PROGRAM_ROOT_FOLDER_FILE: If you want to program design file from the rootfolder <design_name>, set to 1 Attention: it should be only one .bit, .msc or *.bin file in the root folder. Optional Settings: XILINXGIT_DEVICETREE: can be used to generate device tree with SDK Optional Debugging Flags: XIL_CSE_ZYNQ_DISPLAY_UBOOT_MESSAGES: additinal micro uboot messages (Zynq) XIL_CSE_ZYNQ_UBOOT_QSPI_FREQ_HZ: additinal micro uboot programming speed(Zynq)
design_clear_design_folders.cmd	(optional) Attention: Delete "<design_name>/v_log/", "<design_name>/vivado/", "<design_name>/vivado_lab/", "<design_name>/sdsoc/", and "<design_name>/workspace/" directory with related documents! Type "Y" into the command line input to start deleting files
design_run_project_batchmode.cmd	(optional) Create Project with setting from "design_basic_settings.cmd" and source folders. Build all Vivado hardware and software files if the sources are available. Delete "<design_name>/vivado/", and "<design_name>/workspace/hsi/" directory with related documents before Project will created.
Hardware Design
vivado_create_project_guimode.cmd	Create Project with setting from "design_basic_settings.cmd" and source folders. Vivado GUI will be opened during the process. Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Project will created. If old vivado project exists, type "y" into the command line input to start project creation again.
vivado_create_project_batchmode.cmd	(optional) Create Project with setting from "design_basic_settings.cmd" and source folders. Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Project will created. If old vivado project exists, type "y" into the command line input to start project creation again.
vivado_open_existing_project_guimode.cmd	Opens an existing Project "<design_name>/vivado/<design_name>.xpr" and restore Script-Variables.
Software Design
sdk_create_prebuilt_project_guimode.cmd	(optional) Create SDK project with hardware definition file from prebuild folder. It used the *.hdf from: <design_name>/prebuilt/hardware/<board_file_shortname>/. Set <board_file_shortname> and <app_name> in "design_basic_settings.cmd".
Programming
program_flash_binfile.cmd	(optional) For Zynq Systems only. Programming Flash Memory via JTAG with specified Boot.bin. Used SDK Programmer (Same as SDK "Program Flash") or LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the boot.bin from: <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>. Settings are done in "design_basic_settings.cmd".
program_flash_mcsfile.cmd	(optional) For Non-Zynq Systems only. Programming Flash Memory via JTAG with specified <design_name>.mcs. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.mcs from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd".
program_fpga_bitfile.cmd	(optional) Programming FPGA via JTAG with specified <design_name>.bit. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.bit from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd".
labtools_open_project_guimode.cmd	(optional) Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd".

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File Name	Status	Description
Design + Settings
design_basic_settings.sh	available	Settings for the other .cmd files. Following Settings are avaliable: General Settings: (optional) DO_NOT_CLOSE_SHELL: Shell do not closed after processing (optional) ZIP_PATH: Set Path to installed Zip-Program. Currently 7-Zip are supported. IUsed for predefined TCL-function to Backup project. (optional) ENABLE_SDSOC: Enable SDSOC Setting. Currently only for some reference project as beta version! Xilinx Setting: XILDIR: Set Xilinx installation path (Default: /opt/Xilinx/). VIVADO_VERSION: Current Vivado/LabTool/SDK Version (Example:20172018.42). Don't change Vivado Version. Xilinx Software will be searched in: VIVADO (optional for project creation and programming): %XILDIR%/Vivado/%VIVADO_VERSION%/ and for SDSoC on %XILDIR%\SDx\%VIVADO_VERSION%\Vivado\ SDK (optional for software projects and programming): %XILDIR%/SDK\%VIVADO_VERSION%/ LabTools (optional for programming only): %XILDIR%/Vivado_Lab/%VIVADO_VERSION%/ SDSOC (optional): %XILDIR%/SDx/%VIVADO_VERSION%/ Board Setting: PARTNUMBER: Set Board part number of the project which should be created Available Numbers: (you can use ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list) Used for project creation and programming To create empty project without board part, used PARTNUMBER=-1 (use GUI to create your project. No block design tcl-file should be in /block_design) Example TE0726 Module : USE ID \|USE PRODID PARTNUMBER=1 \|PARTNUMBER=te0726-01 Programming Settings(programfile.cmd): SWAPP: Select Software App, which should be configured. Use the folder name of the <design_name>/prebuilt/boot_image/<partname>/* subfolder. The bin,.mcs or .bit from this folder will be used. If you will configure the raw .bit or .mcs .bin from the <design_name>/prebuilt/hardware/<partname>/ folder, use @set SWAPP=NA or @set SWAPP="". Example: SWAPP=hello_world → used the file from prebuilt/boot_image/<partname>/hello_world SWAPP=NA → used the file from <design_name>/prebuilt/boot_image/<partname>/ PROGRAM_ROOT_FOLDER_FILE: If you want to program design file from the rootfolder <design_name>, set to 1 Attention: it should be only one .bit, .msc or *.bin file in the root folder.
design_clear_design_folders.sh	not available	(optional) Attention: Delete "<design_name>/v_log/", "<design_name>/vivado/", "<design_name>/vivado_lab/", "<design_name>/sdsoc/", and "<design_name>/workspace/" directory with related documents! Type "Y" into the command line input to start deleting files
design_run_project_bashmode.sh	not available	(optional) Create Project with setting from "design_basic_settings.cmd" and source folders. Build all Vivado hardware and software files if the sources are available. Delete "<design_name>/vivado/", and "<design_name>/workspace/hsi/" directory with related documents before Project will created.
Hardware Design
vivado_create_project_guimode.sh	available	Create Project with setting from "design_basic_settings.cmd" and source folders. Vivado GUI will be opened during the process. Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Project will created. If old vivado project exists, type "y" into the command line input to start project creation again.
vivado_create_project_bashmode.sh	not available	(optional) Create Project with setting from "design_basic_settings.cmd" and source folders. Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Project will created. If old vivado project exists, type "y" into the command line input to start project creation again.
vivado_open_existing_project_guimode.sh	available	Opens an existing Project "<design_name>/vivado/<design_name>.xpr" and restore Script-Variables.
Software Design
sdk_create_prebuilt_project_guimode.sh	not available	(optional) Create SDK project with hardware definition file from prebuild folder. It used the *.hdf from: <design_name>/prebuilt/hardware/<board_file_shortname>/. Set <board_file_shortname> and <app_name> in "design_basic_settings.cmd".
Programming
program_flash_binfile.sh	not available	(optional) For Zynq Systems only. Programming Flash Memory via JTAG with specified Boot.bin. Used SDK Programmer (Same as SDK "Program Flash") or LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the boot.bin from: <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>. Settings are done in "design_basic_settings.cmd".
program_flash_mcsfile.sh	not available	(optional) For Non-Zynq Systems only. Programming Flash Memory via JTAG with specified <design_name>.mcs. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.mcs from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd".
program_fpga_bitfile.sh	not available	(optional) Programming FPGA via JTAG with specified <design_name>.bit. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.bit from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd".
labtools_open_project_guimode.sh	not available	(optional) Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd".

...

Install Xilinx Vivado Design Suite or Xilinx Vivado Webpack (free license for some FPGA only: see http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html)
(optional) Install Xilinx Vivado LabTools (Lab Edition)
Configure the reference-design:
1. Open “design_basic_settings.cmd” with a text-editor:
    a. Set correct Xilinx Environment:
        @set XILDIR=C:/Xilinx
        @set VIVADO_VERSION=20172018.42
        Program settings will be search in :
        %XILDIR%/VIVADO/%VIVADO_VERSION%/
        %XILDIR%/Vivado_Lab/%VIVADO_VERSION%/
        %XILDIR%/SDK/%VIVADO_VERSION%/
        Example directory: c:/Xilinx/Vivado/20172018.42/
        Attention: Scripts are supported only with predefined Vivado Version!
    b. Set the correct module part-number:
        @set PARTNUMBER=x
        You found the available Module Numbers in <design_name>/board_files/<board_series>_board_files.csv
    c. Set Application name (for programming with batch-files only):
        @set SWAPP=NA
        NA (No Software Project) used *.bit or *.mcs from <design_name>/prebuilt/hardware/<board_file_shortname>
       <app_name> (Software Project) used *.bit or *.mcs or *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
Create all prebuilt files in one step:
2. Run “design_run_project_batchmode.cmd”
(optional to Step 2) Create all prebuilt files in single steps:
3. Run “vivado_create_project_guimode.cmd”:
    A Vivado Project will be create and open in ./vivado
4. Type “TE::hw_build_design” on Vivado TCL-Console:
    Run Synthese, Implement and create Bitfile and optional MCSfile
5. Type “TE::sw_run_hsi” on Vivado TCL-Console:
    Create all Software Applications from <design_name>/sw_lib/apps_list.csv
6. (optional to Step 5) Type “TE::sw_run_sdk” on Vivado TCL-Console:
    Create a SDK Project in <design_name>/workspace/sdk
    Include Hardware-Definition-File, Bit-file and local Software-libraries from <design_name>/sw_lib/sw_apps
Programming FPGA or Flash Memory with prebuilt Files:
7. Connect your Hardware-Modul with PC via JTAG.
With Batch-file:
8. (optional) Zynq-Devices Flash Programming (*.bin):
    Run “program_flash_binfile.cmd”
9. (optional) FPGA-Device Flash Programming (*.mcs):
    Run “program_flash_mcsfile.cmd”
10. (optional) FPGA-Device Programming (*.bit):
      Run “program_fpga_bitfile.cmd”
With Vivado/Labtools TCL-Console:
11. Run “vivado_open_existing_project_guimode.cmd” or “labtools_open_project_guimode.cmd” to open Vivado or LabTools
12. (optional) Zynq-Devices Flash Programming (*.bin):
      Type “TE::pr_program_flash_binfile -swap <app_name>” on Vivado TCL-Console
      Used *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
13. (optional) FPGA-Device Flash Programming (*.mcs):
      Type “TE:: pr_program_flash_mcsfile -swap <app_name>” on Vivado TCL-Console
      Used *.mcs from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
14. (optional) FPGA-Device Programming (*.bit):
      Type “TE:: pr_program_jtag_bitfile -swap <app_name>” on Vivado TCL-Console
      Used *.bit from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>

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Microblaze Firmware (*.elf) can be add to the source folder <design_name>/firmware/<Microblaze IP Instance> or <design_name>/firmware/<BD hierarchie>/<Microblaze IP Instance>.
For MCS-Core use MCS IP Instance Name. This name must use *mcs* or *syscontrol* in the name.

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Date

Revision

Vivado Version

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

	current-version
	current-version
prefix	v.

20172018.42

Page info

	modified-user
	modified-user

2018.2 Work in progress

23 May 2018

v141

2017.4

John Hartfiel

Last Vivado 20174 supported project delivery version

2017-11-03

v.134

2017.2

John Hartfiel

Last Vivado 2017.2 supported project delivery version

2017-09-12

v.131

2017.1

John Hartfiel

Last Vivado 2017.1 supported project delivery version

2017-04-12

v.126

2016.4

John Hartfiel

Last Vivado 2016.4 supported project delivery version

2017-01-16

v.114

2016.2

John Hartfiel

Last Vivado 2016.2 supported project delivery version

2016-06-21

v.83

2015.4

John Hartfiel

Last Vivado 2015.4 supported project delivery version

2013-03-11

v.1

---

Antti Lukats

Initial release

All

Page info

	modified-users
	modified-users

...

Trenz Electronic Documentation

Versions Compared

Old Version 141

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