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| Note |
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This is preliminary based on Vivado 2016.1 release, the "DDR Less" flow should become even easier with the next Vivado releases. Hope remains. |
Step by Step
- In Vivado IPI create a BD and configure PS7 block with no DDR, one UART should be enabled also, even if you do not use UART in your application
- in SDK create FSBL, in main.c add one line, and comment out one line:
#define
...
- XPAR_PS7_DDR_0_S_AXI_BASEADDR
...
- 0
#ifdef
...
- XPAR_PS7_DDR_0_S_AXI_BASEADDR
//Status
...
- =
...
- DDRInitCheck();
...
- Create BOOT.BIN
Thats all, PS will load the FPGA bitstream and then do nothing. There is no need to patch the init tcl script, it does not include the DDR init so it will not freeze.
...
Example DDR less Zynq system debug session, FSBL with JTAG DCC console running on TE0722.
Related Links:
- https://www.xilinx.com/support/answers/56044.html
- http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+Boot+-+Booting+and+Running+Without+External+Memory+Tech+Tip
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