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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512. The Ethernet PHY RGMII interface is connected to the Zynq SoC's PS bank 501 pins MIO16 .. MIO27. Reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the programmable clock generator (U10) pin IN5.
High-speed USB ULPI PHY
Hi-speed USB ULPI PHY (U6) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq SoC's PS bank 501 pins MIO28 .. 39. Reference clock input is supplied from the on-board 52.000000 MHz oscillator (U15).
MAC Address EEPROM
A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.
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