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Template Revision 2.1

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

  • Change List 2.0 to 2.1
    • Fix problem with pdf export and side scroll bar
  • Change List 1.9.1 to 2.0
    • add fix table of content
    • add table size as macro
    • removed page initial creator


Overview

CPLD Device with designator U5: LCMX02-1200HC.

Feature Summary

  • JTAG
  • UART
  • I2C
  • Power
  • Boot Mode
  • Reset
  • SD
  • LED

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank PowerDescription

UART_TXD

in77NONE3.3V

UART0 TX / Sends data to MIO13. MIO13 is connected to B2B JB1 Pin 98. ( HSS console )

UART_RXDout84NONE3.3V

UART0 RX / Recieves data from MIO12. MIO12  is connected to B2B JB1 Pin 100. ( HSS console )

CM0in76UP3.3V

DIP switch S2-2 / used as JTAG Selection/ If CM0 set to high (S2-2 OFF) → Access to CPLD of module otherwise access to FPGA of module.

CM1in75UP3.3VDIP switch S2-1 / Used to change PGOOD pin state /If CM1 set to high (S2-1 OFF) → PGOOD = '1' otherwise '0'
EN1out81NONE3.3VB2B Power Enable
FL_0inout28NONE3.3V LED (D3-red) / Status 
FL_1inout27NONE3.3VLED (D4-green) / Status
FT_B_RXout138NONE3.3VFTDI UART RX (UART1 RX)
FT_B_TX / BDBUS0in139UP3.3VFTDI UART TX (UART1 TX)
JTAGEN---120---3.3VEnable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over S2-3
M_TCKin131NONE3.3VJTAG from/to FTDI
M_TDIin136NONE3.3VJTAG from/to FTDI
M_TDOout137NONE3.3VJTAG from/to FTDI
M_TMSin130NONE3.3VJTAG from/to FTDI
MIO0in94UP3.3VDIP-S4 and B2B JB1 Pin 88. This signal is connected to MODE signal.
MIO12in100NONE3.3VSends data to UART_RX
MIO13out99NONE3.3VRead data from UART_TX 
MIO14out105NONE3.3VReceives data from FT_B_TX of FTDI chip
MIO15in95NONE3.3VSends data to FT_B_RX of FTDI chip
MIO9 out96NONE3.3V SD_CD signal is directed to this signal in firmware. 
MODEout83NONE3.3VDip switch S2-4 is connected to MODE pin ( B2B-JB1-31)
NOSEQ inout78UP3.3VNOSEQ can be set or reset by i2c interface in linux console, if an i2c interface is prepared for this in linux. 
PGOOD inout82UP3.3VPGOOD can be set or reset via CM1 ( dip switch S2-1)
PHY_LED1 out86DOWN3.3V Shows the status of PGOOD, CM0 or MIO0 signals.
PHY_LED1R out92NONE3.3V Shows the status of PGOOD, CM0 or MIO0 signals.
PHY_LED2 out85NONE3.3VShows the status of PGOOD, CM0 or MIO0 signals.
PHY_LED2R out91NONE3.3V Shows the status of PGOOD, CM0 or MIO0 signals.   
PROGMODEout104UP3.3VEnable B2B Module JTAG access to CPLD for Firmware update
RESINout119NONE3.3VModule Reset Pin on B2B connector
S1in114UP3.3VPush Button / Used as module Reset
SD_CD in93UP3.3VForwarded to MIO9
SD_SEL out113NONE3.3VSet to GND / currently_not_used
TCK_Bout1NONE3.3VJTAG from/to Module
TDI_Bout3NONE3.3VJTAG from/to Module
TDO_B / C_TDOin2UP3.3VJTAG from/to Module
TMS_Bout4NONE3.3VJTAG from/to Module
ULED1out117NONE3.3VLED (D1-red) / Shows the status of PGOOD, CM0 or shows the UART1 RX.
ULED2out115NONE3.3VLED (D2-green) / Shows the status of PGOOD, CM0 or shows the UART1 TX.
X16in59UP3.3Vcurrently_not_used
X17out60NONE3.3Vcurrently_not_used
SDA / MIO11inout97UP3.3VI2C Data
SCL /MIO10in98UP3.3VI2C Clock (100kHz)

Functional Description

JTAG

JTAG signals routed directly through the CPLD to module in B2B connector. Access between CPLD and module can be multiplexed via JTAGEN (logical one for CPLD, logical zero for module). TEB2000 CPLD can be selected with JTAGEN (DIP-S2-3). Module FPGA/CPLD access can be switched with PROGMODE which is driven by CM0 (DIP-S2-2).CM0 is pulled up with CPLD.

S2-2S2-3PROGMODE (S2-2)JTAGEN (S2-3)Description
OFFOFF11Access to TE0703 CPLD
OFFON10Access to CPLD of B2B Module
ONOFF01Access to TE0703 CPLD
ONON00Access to FPGA of B2B Module

Note: LED1,2,3,4 are on and PHY LEDs blink slow, if S2-2 is set to OFF.

DIP Switch

DIP Switch S2
S2-1S2-2S2-3S2-4Description
CM1CM0JTAGENMIO0JTAGEN set carrier board CPLD into the chain for firmware update.

EN1

EN1 is set to one.

NOSEQ

NOSEQ pulled up to 3.3V. NOSEQ can be set or reset by i2c interface in linux console, if an i2c interface is prepared for this in linux. 

NOSEQConnected toRelated command in linux consoleDescription
'0'GPIO_output[16]
i2cset -y <related bus> 0x20 0x02 0x00
It is depends on the linux design. For example → i2cset -y 0 0x20 0x02 0x00
'1'GPIO_output[16]
i2cset -y <related bus> 0x20 0x02 0x01
It is depends on the linux design. For example → i2cset -y 0 0x20 0x02 0x01

To read NOSEQ, GPIO_input[16] must be read. To read this bit the following instruction must be executed in linux console:


i2cget -y <related bus> 0x20 0x02

For example --> i2cget -y 0 0x20 0x02

PGOOD

PGOOD pulled up to 3.3V. PGOOD pin can be set or reset by user. If CM1 set to high (S2-1 OFF) , PGOOD will be set to high otherwise PGOOD is set to low.

PGOODConditionDescription
'0'

CM1 = '0'

Dip switch S2-1 ON
'1'CM1 = '1'Dip switch S2-1 OFF

Reset

RESIN is driven by S1 (Push Button). Button is debounced.

Boot Mode

MODE pin is sourced by MIO0. MIO0 connected DIP S2-4 and B2B connector. MIO is pulled up with CPLD and can be set to GND via DIP. PGOOD pin will be used as second select pin for boot mode selection. In this case the following table can be considered:  

S2-1S2-4PGOODMIO0Description
ONON00JTAG boot mode
OFFON10SD Card boot mode, PHY LEDs glow orange
OFFOFF11QSPI boot mode, PHY LEDs glow green

UART

Primary UART:

MIO14 is driven by BDBUS0 (FTDI RX).

BDBUS1 (FTDI TX) is driven by MIO15 .

Secondary UART:

MIO13 is driven by X16.

X17 is driven by MIO12.

SD

SD selection is set to GND (SD Card slot).

MIO9 is switched to SD_CD and its status depends on SD_CD .

LED

LED Priority is order of the description

LEDPrio 0: PowerPrio 1: Modul CPLD access*Prio 2
LED1 (D1-red)Blink, if Power Good is lowONFTDI UART RX
LED2 (D2-green)Blink, if Power Good is lowONFTDI UART TX
LED3 (D3-red)OFFONUser defined with B2B Pin JB2-99
LED4 (D4-green)OFFONUser defined with B2B Pin JB2-90
PHY LEDs (green/orange)Blink orange, if Power Good is lowBlink Green and orangeGreen: Boot Mode set  to QSPI, Orange: Boot Mode set to SD

*Attention: LED1,2,3,4 are on, if S2-2 is set to OFF. If S2-3 is OFF, TE0703 is in chain!

Appx. A: Change History and Legal Notices

Revision Changes

REV02 to REV03

  • Oscillator frequency is changed from 12.09 MHz to 24.18 MHZ.

  •  Access to CPLD of TE0715 with a generic parameter added. (For optional jed file to access CPLD of TE0715 module)

  • PGOOD used as second boot mode selector pin and connected to dip switch S2-1. PGOOD and MODE are boot mode selector pins.

  • S2-1 dip switch (CM1) functionality is changed.In HW PCB REV0 to REV04 is used for SD card detection but in HW PCB REV05 and REV06 is used to set or reset PGOOD.
    • MIO14 is connected to FTDI_RXD directly without depending on PGOOD.

    • CM1 (Dip switch S2-2) has no effect on MIO9 anymore. That means MIO9 is connected to SD_CD only and not to SD_CD and CM1.
      • REV02 to older REV01
    • Enable CPLD access to module CPLD over DIP
    • Add MIO0, SD_SEL, SD_CD, NOSEQ, PGOOD, 2LEDs, PHY LEDs
    • Debounce button
    • More status LED functionality

    Document Change History

    To get content of older revision  got to "Change History"  of this page and select older document revision number.

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    • Note this list must be only updated, if the document is online on public doc!
    • It's semi automatically, so do following

      • Add new row below first

      • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

      • Metadata is only used of compatibility of older exports


    REV03REV05, REV06 REV03 SC-PGM-TE0703-0506_CARRIER-03_20220815.zip)
  • PGOOD as secondboot mode select pin
  • TE0715 CPLD programming is possible

    • v.11

    DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

    Page info
    modified-date
    modified-date
    dateFormatyyyy-MM-dd

    Page info
    infoTypeCurrent version
    prefixv.
    typeFlat

    		REV01

    REV01 

    Page info
    modified-user
    modified-user

    • REV01 release
    • Firmware release (
    2019-11-08v.13REV02REV02*,REV03*,REV04*,REV05, REV06
    *some IOs are not connected *SD_CD not available, set S2-1 to on    		John Hartfiel
    • Typo
    • Note PCB REV06 support

    2017-10-13

    		REV02

    REV02*,REV03*,REV04*,REV05
    *some IOs are not connected
    *SD_CD not available, set S2-1 to on

    John Hartfiel

    • REV 02 finished
    2016-04-11

    v.1

    		REV02

    REV02*,REV03*,REV04*,REV05
    *some unused IOs are not connected
    *SD_CD not available, set S2-1 to on

    John Hartfiel

    • Initial release
    AllJohn Hartfiel
    • *.zip) 

    Appx. B: Legal Notices

    Include Page
    IN:Legal Notices
    IN:Legal Notices




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