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Overview

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Notes :

Refer to http://trenz.org/teg2000-info for the current online version of this manual and other available documentation.

This page describes briefly how to generate the fpga configuration file (Bitstream/cfg file) from one of the provided test projects and how to program the FPGA. For a more detailed description of the tools follow the Quick start section of colognechip ug1002

Key Features

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Notes :

  • Add basic key features, which can be tested with the design


Excerpt
  • USB(JTAG/UART)
  • LED

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description
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DateVivadoProject BuiltAuthorsDescription



Waldemar Hanemann
  • initial release



Release Notes and Know Issues

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IssuesDescriptionWorkaroundTo be fixed version
No known issues---------


Requirements

Software

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Notes :

  • list of software which was used to generate the design


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SoftwareVersionNote
Yosys--0.37+39needed for RTL Synthesissynthesis
GateMate EasyConvert Place&Route2024.02--001needed for implementation and Bitstream generation
openFPGALoader--v.0.11.0needed for loading bitstream into FPGA


Hardware

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Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *

Design supports following modules:

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TEG2000-01-P001--REV01--16MB--

*used as reference


Design supports following carriers:

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Carrier ModelNotes
TE0703*We only support TE0703 up until now.

*used as reference

Additional HW Requirements:

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Additional HardwareNotes


*used as reference

Content

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  • content of the zip file

For general structure and usage of the reference design, see Project Delivery - AMD devices

Design Sources

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TypeLocationNotes

Additional Sources

Toolchain<project folder>\binscript-based tools for synthesis, implementation,
bitfile generation and programming
fpga project

<project folder>\workspace\blink\log

<project folder>\workspace\blink\net

<project folder>\workspace\blink\sim

<project folder>\workspace\blink\src

.bat scripts can be used for synthesis & implementation & programming


Additional Sources

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TypeLocationNotes










Prebuilt

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  • prebuilt files
  • Template Table:

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      Boot Script-File*.scr

      Distro Boot Script file

      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
      Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




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File

File-Extension

Description

Constraint-File*.ccfFPGA pin constraint for pin-location, naming, input-output setting etc. 
Design source-files*.v   *.vhdhdl design files describing the fpga functional description and I/O signals
Config File *.cfgConfig File Data for FPGA. Comments included. 

File

File-Extension

Description

BIT-File*.bitFPGA (PL Part) Configuration File.cfg????


Download

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

It's recommended to use TE prebuilt files for first launch.


→ HOW TO OPEN PROJECT and PROGRAM ← 


Launch

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Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Get prebuilt boot binaries



QSPI-Boot mode


JTAG

Not used on this example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Info

    Note: See TRM of the Carrier, which is used.


  4. Power On PCB

    Expand
    titleboot process






System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...



Constraints

Basic module constraints

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titleMF8A18_SoC.ccf
## blink.ccf
#
# Date: 2022-10-21
#
# Format:
# <pin-direction> "<pin-name>" Loc = "<pin-location>" | <opt.-constraints>;
#
# Additional constraints can be appended using the pipe symbol.
# Files are read line by line. Text after the hash symbol is ignored.
#
# Available pin directions:
#
# Pin_in
#   defines an input pin
# Pin_out
#   defines an output pin
# Pin_inout
#   defines a bidirectional pin
#
# Available pin constraints:
#
# SCHMITT_TRIGGER={true,false}
#   enables or disables schmitt trigger (hysteresis) option
# PULLUP={true,false}
#   enables or disables I/O pullup resistor of nominal 50kOhm
# PULLDOWN={true,false}
#   enables or disables I/O pulldown resistor of nominal 50kOhm
# KEEPER={true,false}
#   enables or disables I/O keeper option
# SLEW={slow,fast}
#   sets slew rate to slow or fast
# DRIVE={3,6,9,12}
#   sets output drive strength to 3mA..12mA
# DELAY_OBF={0..15}
#   adds an additional delay of n * nominal 50ps to output signal
# DELAY_IBF={0..15}
#   adds an additional delay of n * nominal 50ps to input signal
# FF_IBF={true,false}
#   enables or disables placing of FF in input buffer, if possible
# FF_OBF={true,false}
#   enables or disables placing of FF in output buffer, if possible
# LVDS_BOOST={true,false}
#   enables increased LVDS output current of 6.4mA (default: 3.2mA)
# LVDS_TERM={true,false}
#   enables on-chip LVDS termination resistor of nominal 100Ohm, in output mode only
#
# Global IO constraints can be set with the default_GPIO statement. It can be
# overwritten by individual settings for specific GPIOs, e.g.:
#   default_GPIO | DRIVE=3; # sets all output strengths to 3mA, unless overwritten
#

Pin_in   "clk"  Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true;
Pin_out  "UART_TXD"   Loc = "IO_SB_A4"; # MIO15
Pin_out  "led"  Loc = "IO_SB_B4"; # one board LED
#Pin_in   "resetn"   Loc = "IO_EA_B2"; # TEB0707 user button active high!
#Pin_in   "resetn"   Loc = "IO_SB_B6"; # permanent 1
#Pin_in   "resetn"   Loc = "IO_SB_B5"; # permanent 0











Additional Software

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No additional software is needed.

App. A: Change History and Legal Notices

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Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

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    • Metadata is only used of compatibility of older exports


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DateDocument Revision

Authors

Description

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--


Legal Notices

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