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Reference-Design: Getting Started

• Install Xilinx Vivado Design Suite or Xilinx Vivado Webpack (free license for some FPGA only: see http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html)
  (optional) Install Xilinx Vivado LabTools (Lab Edition)
• Configure the reference-design:
  1. Open “design“design_basic_settings.cmd” cmd” with a text-editor:
      a. Set correct Xilinx Environment:
          @set XILDIR=C:/Xilinx
          @set VIVADO_VERSION=2015.4
          Program settings will be search in :
          %XILDIR%/VIVADO/%VIVADO_VERSION%/
          %XILDIR%/Vivado_Lab/%VIVADO_VERSION%/
          %XILDIR%/SDK/%VIVADO_VERSION%/
          Example directory: c:/Xilinx/Vivado/2015.4/
          Attention: Scripts are supported only with predefined Vivado Version!
      b. Set the correct module part-number:
          @set PARTNUMBER=x
          You found the available Module Numbers in ./board_files/<board_series>_board_files.csv
      c. Set Application name (for programming with batch-files only):
          @set SWAPP=NA
          NA (No Software Project) used *.bit or *.mcs from <design_name>/prebuilt/hardware/<board_file_shortname>
         <app_name> (Software Project) used *.bit or *.mcs or *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
• Create all prebuilt files in one step:
  2. Run “design“design_run_project_batchmode.cmd”cmd”
• (optional to Step 2) Create all prebuilt files in single steps:
  3. Run “vivado“vivado_create_project_guimode.cmd”cmd”:
      A Vivado Project will be create and open  in ./vivado
  4. Type “TE“TE::hw_build_design” design” on Vivado TCL-Console:
      Run Synthese, Implement and create Bitfile and optional MCSfile
  5. Type “TE“TE::sw_run_hsi” hsi” on Vivado TCL-Console:
      Create all Software Applications from ./sw_lib/apps_list.csv
  6. (optional to Step 5) Type “TE“TE::sw_run_sdk” sdk” on Vivado TCL-Console:
      Create a SDK Project in <design_name>/workspace/sdk
      Include Hardwaredefinition, Bitfile annd local Software libraries from  in <design_name>/sw_lib

• Programming FPGA or Flash Memory with prebuilt Files:
  7. Connect your Hardware-Modul with PC via JTAG.
  With Batch-file:
  8. (optional) Zynq-Devices Flash Programming (*.bin):
      Run “program“program_flash_binfile.cmd”cmd”
  9. (optional) FPGA-Device Flash Programming (*.mcs):
      Run “program“program_flash_mcsfile.cmd”cmd”
  10. (optional) FPGA-Device Programming (*.bit):
        Run “program“program_fpga_bitfile.cmd”cmd”
  With Vivado/Labtools TCL-Console:
  11. Run “vivado“vivado_open_existing_project_guimode.cmd” cmd” or “labtools“labtools_open_project_guimode.cmd” cmd” to open Vivado  or LabTools
  12. (optional) Zynq-Devices Flash Programming (*.bin):
        Type “TE“TE::pr_program_flash_binfile -swap <app_name>” name>” on Vivado TCL-Console
        Used *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
  13. (optional) FPGA-Device Flash Programming (*.mcs):
        Type “TE“TE:: pr_program_flash_mcsfile -swap <app_name>” name>” on Vivado TCL-Console
        Used *.mcs from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
  14. (optional) FPGA-Device Programming (*.bit):
       Type “TE“TE:: pr_program_jtag_bitfile -swap <app_name>” name>” on Vivado TCL-Console
       Used *.bit from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>

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1. Unzip project files
2. Rename basefolder (basefolder name is used as project name)
3. Edit design_basic_settings.cmd
   1. Select the correct Xilinx Program path (See: Windows Command Files → design_basic_settings.cmd)
   2. Select the correct board part number for your PCB  (See: Windows Command Files → design_basic_settings.cmd)
   3. Other settings are optional  (See: Windows Command Files → design_basic_settings.cmd)
4. Excecute vivado_create_project_guimode.cmd or vivado_create_project_batchmode.cmd to generate a vivado project with the predefined Block Design from the Block Design folder
5. Open Vivado with vivado_open_existing_project_guimode.cmd (if you use vivado_create_project_guimode.cmd on step 4, you didn't need this)
6. Open the Block Design and create your own design inside this Block Design.
7. Backup your Block Design as tcl-script: Type "TE::hw_blockdesign_export_tcl" on Vivado Tcl Console. The old one will be overwritten.
8. Build your Design...

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• Variant 1 (recommended):
  • Start the project with the predefined command file (vivado_open_existing_project_guimode.cmd.cmd) respectively LabTools with (labtools_open_project_guimode.cmd)
• Variant 2:
  • Create your own Initialisation Button on the Vivado GUI:
    • Tools → Customize Commands → Customize Commands...
    • Push
    • Type Name ex.: Init Scripts
    • Press Enter
    • Select Run command and insert:
      
      • for Vivado: cd [get_property DIRECTORY [current_project]]; source -notrace "../scripts/reinitialise_all.tcl"
      • for LabTool: cd [pwd]; source -notrace "../scripts/reinitialise_all.tcl"
        
    • Press Enter
    • A new Button is shown on the Vivado Gui: All Scripts are reinitialised, if you press this Button.
      
• Variant 3:
  • Reinitialise Script on Vivado TCL-Console:
    • Type: source ../scripts/reinitialise_all.tcl
      

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