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Scroll Title
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titleRecommended Operating Conditions

This TRM is generic for all variants.

Variants of modules are described here: Article Number Information

Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C

Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C

Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C

The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

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ParameterMinMaxUnitsReference Document
VIN supply voltage3.1353.45V-
HR I/O banks supply voltage (VCCO)1.143.465VXilinx datasheet DS181
HR I/O banks input voltage-0.20VCCO + 0.20VVXilinx datasheet DS181
Voltage on module JTAG pins0VCCO_0 + 5%VXilinx datasheet DS181

This TRM is generic for all variants.

Variants of modules are described here: Article Number Information

Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C

Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C

Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C

Xilinx datasheet DS181
Voltage on module JTAG pins0VCCO_0 + 5%VXilinx datasheet DS181
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.


Physical Dimensions

  • Module size: 40 mm × 30 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm

  • PCB thickness: 1.6 mm

  • Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.

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titleDocument change history

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v.78

Date

Revision

Authors

Description

2021-04-07

Thomas Steffens
  • changed operating conditions

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dateFormatyyyy-MM-dd

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  • changed operating conditionsVCCIO_0 voltages and connection

2019-03-04v55John Hartfiel
  • Restore and modify v.50
  • Correction max IO count on key features
  • Change history table
  • typo correction
2019-01-07v.50John Hartfiel
  • Updated to TRM version 2.2
  • Style modifications

2018-09-19

v.48Martin Rohrmüller
  • Updated to TRM version 2.1
  • Updated B2B Connectors
  • Style modifications
2018-09-17

v.38

Martin Rohrmüller
  • Added power rail section
  • Added Rev 02 Flash PCN
  • Corrected table headings
2018-09-17v.36Martin Rohrmüller

  • Update to TRM version 2.0 with DrawIO Figures

  • Added Figure Power Distribution
2018-04-04

v.35

Martin RohrmüllerCorrected clock net designator in table.
2017-05-28

v.27

Jan Kumann
  • Board-to-Board I/O section added.
  • New physical dimensions images.
  • Documents sections rearranged.
2017-03-20

v.26

John Hartfiel
  • Notes on Clocking section.
2017-01-27v.25Jan Kumann
  • New block diagram.
2016-12-01

v.17

Jan Kumann
  • Changes in the document structure, few corrections.
2016-11-18
v.14

Thorsten Trenz, Emmanuel Vassilakis

  • Hardware revision 02 specific changes.

2016-06-01

v.9

Antti Lukats

  • Initial version.
--all

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