| 2023-12-01 | 03 | - Changed DCDC (U24, U25, U26) from EN5311QI to MPM3834C.
- Changed DCDC (U23) from EN6347QI to MPM3860GQW-Z.
- Changed load switch (Q1) from TPS27082LDDCR to MP5077GG-Z.
- Added power supervisor (U4).
- Changed ferrid bead (L2... L7, L10... L13) from BKP0603HS121-T to MPZ0603S121HT000.Changed power net name from 1.5V to DDR_VDD.
- Changed power sequencing.
- Voltage supervisor (U4) enables 1V voltage rail (DCDC U23) via signal EN_Module.
- 1V DCDC (U23) enables 1.8V voltage rail (DCDC U25) via signal PG_1V0.
- 1.8V DCDC (U25) enables 2.5V (DCDC U24) and DDR_VDD (DCDC U26) voltage rails via signal PG_1V8.
- Voltage rail 3.3V (load switch Q1) is logical AND-enabled via
- power good signal PG_2V5_3V3 from voltage rail 2.5V DCDC (U24) and DDR_VDD DCDC (U26) via diode (D4)
- CPLD (U6) signal EN_3V3 via diode (D5).
- Added level shifter in signal FPGA_IO (U7, C185, C186) to separate power domains. Added resistor R91 as fallback.
- Added diode D3 between U21 pin 3 net nRST_in and voltage rail 3.3V.
- Added option to improve noise immunity for signal nRST_in via capacitor C187 (default: not assembled).
- Connected exposed pad to GND for SDIO port expander (U15).
- Added decoupling capacitors:
- C166 for U2I.
- C178 for U2H.
- C167 and C173 for U11.
- C168... C171 for U3C.
- C172 and C179 for U5B.
- C174 for U15.
- C175 for U8.
- C176 for U9.
- C177 for U20.
- Changed 10 µF capacitors (C36, C86) to 22 µF.
- Changed 22 µF capacitors (C117, C121, C125, and C127) from size 0805 to 0603.
- Changed capacitor C144 from 470 nF, 6.3 V, X5R, 20 % to 100 nF, 16 V, X7R, 10 %.
- Pulled-up board revision signal (U2D pin H17) and added board revision documentation.
- Changed fiducials to standard fiducials.
- Removed serial number S/N.
- Added testpoints TP1...TP41.
- Added serial number box on bottom overlay.
- Changed signal trace length.
- Added revision history, block and power overview and additional information. Updated page count and order.
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