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Assembly options for cost or performance optimization available upon request.
Signals, Interfaces and Pins
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Note |
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JTAGSEL pin in J2 should be kept low or grounded for normal operation. |
Clocking
Clock | Frequency | IC | FPGA | Notes |
---|---|---|---|---|
PS CLK | 33.3333 MHz | U14 | PS_CLK | PS Subsystem main clock |
10/100/1000 Mbps ETH PHY reference | 25 MHz | U10 | - | |
USB PHY reference | 52 MHz | U12 | - |
Processing System (PS) Peripherals
Peripheral | IC | Designator | PS | MIO | Notes |
---|---|---|---|---|---|
EEPROM I2C | 24AA025E48T-I/OT | U8 | I2C0 | MIO10, MIO11 | MAC Address |
EEPROM I2C | 24AA025E48T-I/OT | U9 | I2C0 | MIO10, MIO11 | MAC Address |
EEPROM I2C | 24AA025E48T-I/OT | U20 | I2C0 | MIO10, MIO11 | MAC Address |
RTC | ISL12020MIRZ | U22 | I2C0 | MIO10, MIO11 | Temperature compensated real time clock |
RTC Interrupt | ISL12020MIRZ | U22 | GPIO | MIO46 | Real Time Clock Interrupt |
SPI Flash | S25FL256SAGBHI20 | U13 | QSPI0 | MIO1..MIO6 | |
Ethernet0 10/100/1000 Mbps PHY | 88E1512-A0-NNP2I000 | U3 | ETH0 | MIO16...MIO27 | |
Ethernet0 10/100/1000 Mbps PHY Reset | GPIO | MIO51 | |||
Ethernet1 10/100 Mbps PHY | KSZ8081MLXCA | U17 | - | (EMIO) | |
Ethernet1 10/100 Mbps PHY Reset | - | (EMIO) | |||
Ethernet2 10/100 Mbps PHY | KSZ8081MLXCA | U19 | - | (EMIO) | |
Ethernet2 10/100 Mbps PHY Reset | - | (EMIO) | |||
USB | USB3320C-EZK | U11 | USB0 | MIO28...MIO39 | |
USB Reset | GPIO | MIO49 | |||
e-MMC (embedded e-MMC) | MTFC4GMVEA-4M IT | U5 | SDIO0 | MIO40...MIO45 | depending on state of pin MIO48 'SEL_SD' |
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Default MIO mapping:
MIO | Configured as | B2B | Notes |
---|---|---|---|
0 | GPIO | J2-87 | B2B |
1 | QSPI0 | - | SPI Flash-CS |
2 | QSPI0 | - | SPI Flash-DQ0 |
3 | QSPI0 | - | SPI Flash-DQ1 |
4 | QSPI0 | - | SPI Flash-DQ2 |
5 | QSPI0 | - | SPI Flash-DQ3 |
6 | QSPI0 | - | SPI Flash-SCK |
7 | GPIO | - | Red LED D8 |
8 | - | - | - |
9 | GPIO | J2-88 | B2B |
10 | I2C0 SDA | J2-90 | B2B |
11 | I2C0 SCL | J2-92 | B2B |
12 | I2C1 SDA | J2-93 | B2B (SDA on-board I2C, also configurable as GPIO by user) |
13 | I2C1 SCL | J2-95 | B2B (SCL on-board I2C, also configurable as GPIO by user) |
14 | USART0 RX | J2-94 | B2B (RX on-board UART, also configurable as GPIO by user) |
15 | USART0 TX | J2-96 | B2B (TX on-board UART, also configurable as GPIO by user) |
16..27 | ETH0 | RGMII | |
28..39 | USB0 | ULPI | |
40 | SDIO0 | J2-100 | B2B depending on state of pin MIO48 'SEL_SD' |
41 | SDIO0 | J2-102 | B2B depending on state of pin MIO48 'SEL_SD' |
42 | SDIO0 | J2-104 | B2B depending on state of pin MIO48 'SEL_SD' |
43 | SDIO0 | J2-106 | B2B depending on state of pin MIO48 'SEL_SD' |
44 | SDIO0 | J2-108 | B2B depending on state of pin MIO48 'SEL_SD' |
45 | SDIO0 | J2-110 | B2B depending on state of pin MIO48 'SEL_SD' |
46 | GPIO | - | RTC Interrupt |
47 | - | - | - |
48 | GPIO | SEL_SD | select source between e-MMC / baseboard SD-Card |
49 | GPIO | - | USB Reset |
50 | GPIO | - | ETH0 Interrupt |
51 | GPIO | - | ETH0 Reset |
52 | ETH0 | - | MDC |
53 | ETH0 | - | MDIO |
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Bank | Type | Jx | IO count | IO Voltage | Notes |
---|---|---|---|---|---|
500 | MIO | J2-87 J2-88 | 2 | 3,3 V | MIO0, MIO9 |
500 | MIO | J2-93 J2-95 J2-94 J2-96 | 4 | 3,3 V | configured as I2C1 and USART0 by default, configurable as GPIO by user |
13 | HR | J1 | 48 | user | |
33 | HR | J1 | 48 | user | |
35 | HR | J2 | 30 | 3,3 V | |
34 | GPIO | J2 | 10 | 2,5 V | configured as DISP_RX by default, configurable as GPIO by user |
For detailed information about the pin out, please refer to the Master Pinout Table.
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LED | Color | Connected to | Notes |
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D1 | red | System Controller | Global Status LED |
D2 | green | DONE | Inverted DONE, ON when FPGA not configured |
D8 | red | MIO7 | OFF when PS7 not booted and not controlling MIO7 by software, else user controlled |
Note |
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LED D2 is connected to the FPGA Done pin and will go off as soon as PL is configured. This LED will not operate if the |
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System Controller can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module. |
Ethernet
The TE0715 TE0729 is populated equipped with a Marvell Alaska 88E1512 Gigabit Ethernet PHY (U3). The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling.
SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3J2.
The reference clock input of the PHY is supplied from an on board 25MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).
PHY connection:
PHY PIN | ZYNQ PS | ZYNQ PL | Notes | |
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MDC/MDIO | MIO52, MIO53 | - | - | |
LED0 | - | J3 | can be routed via PL to any free PL I/O pin- | pin J2-57 in B2B connector |
LED1 | - | K8 | can be routed via PL to any free PL I/O pin- | pin J2-59 in B2B connector |
LED2/Interrupt | MIO46 | - | - | |
CONFIG | - | - | By default thePin connected to GND, PHY Address is strapped to 0x00 | alternate configuration is possibleby default |
RESETn | MIO50MIO51 | - | - | |
RGMII | MIO16..MIO27 | - | - | |
SGMII | - | - | on B2B J2 connector | |
MDI | - | - | on B2B |
Note: LED1 is connected to PL via level-shifter implemented in system controller CPLD.
USB
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J2 connector |
USB
The USB PHY USB3320 from Microchip is used on the TE0715TE0729. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V.
The reference clock input of the PHY is supplied from an on board 52MHz oscillator (U15U12).
PHY connection:
PHY Pin | Zynq Pin | B2B Name | Notes |
---|---|---|---|
ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY |
REFCLK | - | - | 52MHz from on board oscillator (U15U12) |
REFSEL[0..2] | - | - | 000 GND, select 52MHz reference Clock |
RESETB | MIO51MIO49 | - | Active low reset |
CLKOUT | MIO36 | - | Connected to 1.8V selects reference clock operation mode |
DP,DM | - | OTG_D_P, OTG_D_N | USB Data lines |
CPEN | - | VBUS_V_EN | External USB power switch active high enable signal |
VBUS | - | USB_VBUS | Connect to USB VBUS via a series resistor. Check reference schematic |
ID | - | OTG_ID | For an A-Device connect to ground, for a B-Device left floating |
The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
RTC
An Intersil temperature compensated real time clock IC ISL12020M ISL12020MIRZ is used for timekeeping (U16U22). Battery voltage must be supplied to the module from the main board.
Battery backed registers are accessed at I2C slave address 0x6F???.
General purpose RAM is accessed at I2C slave address 0x57???.
This RTC IC is supported in Linux so it can be used as hwclock device.
MAC-Address EEPROMs
Three Microchip 24AA025E48 EEPROMs (U8, U9, U20) are used on the TE0729. They contain globally unique 48-bit node addresses, that are compatible with EUI-48(TM) and EUI-64(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50 for MAC-Address1 (U8), 0x81 for MAC-Address1 (U9), 0x82 for MAC-Address1 (U20).
Power
For startup, a power supply with minimum current capability of 3A is recommended.
VIN and 3.3VIN can be connected to the same source (3.3 V).
Power Supplies
Vin | 3.3 V to 5.5 V | Typical 200 mA, depending on customer design and connections |
Vin 3.3V | 3.3 V | Typical 50 mA, depending on customer design and connections |
Bank Voltages
Bank | Voltage | max. Value | note |
---|---|---|---|
501 | 1,8 V | - | ETH0 / USB0 / SDIO0 |
500 | 3,3 V | - | SPI / I2C / UART |
502 | 1,5 V | - | DDR3-RAM |
13 | user | 3,3 V | connected to 3,3V by default by 0 Ohm Resistor R36 |
33 | user | 3,3 V | connected to 3,3V by default by 0 Ohm Resistor R55 |
34 | 2,5 V | - | ETH / DISP |
35 | 3,3 V | - | GPIO |
Initial Delivery state