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HDL files cane be saved in the subfolder "<design_name>/hdl/" or "<design_name>/hdl/<shortname>". They will be loaded automatically on project creation. Available formats are *.vhd, *.v and *.sv.  A own top-file must be specified with the name "<design_name>_top.v" or "<design_name>_top.vhd".

 To use source file in simulation onlyset file attributes, the name must include "_simonly_" ,  for synthese simulation only and "_synonly_" for synthese only.

RTL-IP-cores (*.xci). can be saved in the subfolder "<design_name>/hdl/xci" or "<design_name>/hdl/xci/<shortname>". They will be loaded automatically on project creation.

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