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changes.mady.by.user Martin Rohrmüller

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changes.mady.by.user Mohsen Chamanbaz

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Scroll Title
anchorTable_OBP_DIS
titleDip-Switches

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SwitchONOFFNotes
S2-1Set PGOOD pin to low ('0') / Force CD Pin pin to module to GNDhigh impedance ('Z')Set PGOOD pin to high ('1') / Set CD pin set CD Pin to module to SD_CD PinpinTE0703 CPLD - CC703S#CC703S-BootMode /  TE0703 CPLD - CC703S#CC703S-SD
S2-2Module FPGA  JTAG access ( if S2-3 ON)Module CPLD JTAG access ( if S2-3 ON)TE0703 CPLD - CC703S#CC703S-JTAG
S2-3Module FPGA/CPLD  JTAG access (  depends on S2-32)Carrier CPLD  JTAG accessTE0703 CPLD - CC703S#CC703S-JTAG
S2-4 Boot Boot from SD Card (set Pin Set pin to GND)Boot from QSPI flash on module (set Pin Set pin to VDD)

TE0703 CPLD - CC703S#CC703S-BootMode
Boot Mode also depends on module.


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Date

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infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

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infoTypeModified by
typeFlat
showVersionsfalse

  • Changing in the dip-switches table because of updating of CPLD firmware (CPLD Firmware REV03)
2019-10-07v.43Martin Rohrmüller
  • updated to REV06
  • updated to TRM style 2.12

2018-06-13


v.29

Ali Naseri
  • updating operating conditions
2017-02-07v.28John Hartfiel
  • Add DIP setting description
2017-11-09v.26John Hartfiel
  • add B2B connector section
2017-02-21

v.19


Jan Kumann
  • New block diagram.
2017-02-02

v.16

Jan Kumann
  • New board image with silk screen pin markings for VG96 connectors J1 and J2.
2016-12-22

v.14

Jan Kumann
  • Block diagram added.
2016-12-08
v.10

Jan Kumann

  • Document structure revised.
2016-12-05

v.5

John Hartfiel
  • Corrected Boot Mode table.
2016-09-06

v.1

Jan Kumann, John Hartfiel

  • Initial document.

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