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  • This line was added.
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  • Formatting was changed.
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  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"

Template Change history:

DateVersionChangesAuthor

4.2
  • Changes Xilinx to AMD
ED

4.1
  • Minor changes
    • Notes
    • Tables
ED

4.0
  • Rework for smaller TRM which can be generated faster
    • Reduce Signal Interfaces Pin
    • Reduce On Board Periphery
    • Reduce Power
    • Move Configuration Signals from Overview to own section
JH

3.12
  • Version History
    • changed from list to table
  • all
    • changed title-alignment for tables from left to center
ma

3.11
  • update "Recommended Operating Conditions" section


3.1
  • New general notes for temperature range to "Recommended Operating Conditions"


3.02
  • add again fix table of content with workaround to use it for pdf and wiki
  • Export Link for key features examples
    • Notes for different Types (with and without Main FPGA)
  • Export Link for Signals, Interfaces and Pins examples
    • Notes for different Types (Modul, Modul Hybrid, Evalboard, Carrier)


3.01
  • remove fix table of content and page layout ( split page layout make trouble with pdf export)
  • changed and add note to signal and interfaces, to on board periphery section
  • ...(not finished)


3.00
  • → separation of Carrier/Module and evaluation kit TRM


2.15
  • add excerpt macro to key features


2.14
  • add fix table of content
  • add table size as macro


Custom_table_size_100

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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        title-alignmentcenter
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
        anchorTable_tablename
        title-alignmentcenter
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
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        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistent across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchor from external : <page url>#<pagename without space characters>-<anchorname>


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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Scroll Ignore

Download PDF version of this document.

Overview

Trenz Electronic TEM0007 module is an industrial-grade FPGA micromodule integrating a Microsemi Polarfire SoC FPGA, Gigabit Ethernet PHY, USB 2.0 PHY, LPDDR4 SDRAM, SPI Flash memory for configuration and operation, and power supply. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.

Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

See examples for different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt
  • SoC/FPGA
    • Device: MPFS250T / MPFS160T / MPFS095T / MPFS025T 1)
    • Device Family: -T / -TL / -TS / -TLS 1)
    • Speedgrade: Blank / -1 1)
    • Temperature Range: Extended / Industrial 1)
    • Package: FCVG484
  • RAM/Storage
    • 1 GByte LPDDR4 SDRAM 2)
    • 64 MByte SPI Flash Memory 2)
    • EEPROM with MAC address
  • On Board
    • System Controller CPLD
    • Gigabit Ethernet PHY
    • USB 2.0 ULPI Transceiver
    • Oscillator
  • Interface
    • 3 x B2B Connector (LSHM)
      • up to 118 FPGA IOs

        • GPIO: 84
        • HSIO: 34
      • up to 14 MSSIO

      • 1 SGMII
      • 4 MGT
      • SDIO, USB, ETH, UART, I2C, JTAG, CONFIG
  • Power
    • 3.3 V power supply via B2B Connector needed 3).
  • Dimension
    • 40 mm x 50 mm
  • Notes
    1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design. Attention: IO number connected to B2B connector depends on the used device!
    2) Please, take care of the possible assembly options.
    3) A higher or lower input voltage may be possible.

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram


Note

All created DrawIOs  should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD



Scroll Title
anchorFigure_OV_BD
title-alignmentcenter
titleTEM0007 block diagram


Scroll Ignore

draw.io Diagram
bordertrue
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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photos, Please refer to "Diagram Drawing Guidline" .


Scroll Title
anchorFigure_OV_MC
title-alignmentcenter
titleTEM0007 main components


Scroll Ignore

draw.io Diagram
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  1. Microsemi Polarfire SoC, U2
  2. LPDDR4 SDRAM, U6
  3. Ethernet Transceiver, U7
  4. USB Transceiver, U11
  5. System Controller CPLD, U1
  6. B2B Connector, JM1, JM2, JM3
  7. EEPROM, U10
  8. Serial NOR Flash, U3

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Scroll Title
anchorTable_OV_IDS
title-alignmentcenter
titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

LPDDR4 SDRAM

not programmed

SPI NOR Flash

not programmed
EEPROMnot programmed besides factory programmed MAC address
System Controller CPLD, U1Standard firmwareSee TEM0007 CPLD.


Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
  • Table with all connectors and Designator
  • List of different interfaces per connector
  • IO CNT (for FPGA IOs where functionality can be changed by customer)


Connectors

Scroll Title
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titleBoard Connectors

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Connector TypeDesignatorInterfaceIO CNTNotes
B2BJM1GPIOup to 48 SE / 24 DIFFonly 40 SE / 20 DIFF for MPFS025 variants
B2BJM1MSSIO2 x MSSIO
B2BJM1I2C or MSSIOI2C or 2 x MSSIO
B2BJM1SDIO or MSSIOSDIO or 6 x MSSIO
B2BJM1UART or MSSIO2 x UART or 4 x MSSIO
B2BJM1ETH - MDIETH
B2BJM2HSIO18 SE / 9 DIFF
B2BJM2GPIOup to 36 SE / 18 DIFFonly 8 SE / 4 DIFF for MPFS025 variants
B2BJM2CFGJTAG
B2BJM3HSIO16 SE / 8 DIFF
B2BJM3SGMII1 x SGMII (RX/TX)
B2BJM3MGT FPGA4 x MGT (RX/TX)
B2BJM3MGT CLK2 x MGT CLK
B2BJM3USBUSB


Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section.

Example:

Test PointSignalNotes1)
TP1PWR_PL_OK

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Scroll Title
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titleTest Points Information

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Test PointSignalNotes
TP1+3.3V
TP2+2.5V
TP3+2.5V_XCVR
TP4+1.8V
TP5-Signal at U17 pin 3. See schematics.
TP6+1.1V_LPDDR4
TP7+1.0V
TP8VDDAUX1
TP9AVDD18
TP10AVDD33
TP11DVDD1V0
TP12VCCIOB_SW
TP13+2.5V_VDDA
TP14+1.0V_VDDA
TP15+2.5V_VDD

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/InterfaceDesignatorConnected ToNotes
ETH PHYU10
  • B2B connector J1
  • SoC MIO
Gigabit ETH PHY


Scroll Title
anchorTable_OBP
title-alignmentcenter
titleOn board peripherals

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Chip/InterfaceDesignatorConnected ToNotes

System Controller CPLD

U1

B2B
DCDC
SoC
Power Monitor


Gigabit Ethernet

U7

SoC - MSS
B2B - JM1


USB PHY

U11

SoC - MSS
B2B -JM3


LPDDR4 SDRAM

U6SoC - MSS

EEPROM

U10SoC - MSS

SPI Flash Memory

U3SoC - MSS

Oscillator

U4SoC - MSS
OscillatorU5Soc - FPGA
Oscillator
U8ETH PHY
OscillatorU12USB PHY


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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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  • Overview  all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
  • In case it's connected to CPLD always link to CPLD description and add not from the  current implementation here(in case it's available)
Scroll Title
anchorTable_OV_CNTRL
title-alignmentcenter
titleController signal.

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Connector+Pin

Signal Name

Direction1)Description
JM1-7NOSEQIN/OUTSee 4 x 5 SoM Integration Guide and TEM0007 CPLD.
JM1-28SC_EN1INSee 4 x 5 SoM Integration Guide and TEM0007 CPLD.
JM1-30SC_PGOODIN/OUTSee 4 x 5 SoM Integration Guide and TEM0007 CPLD.
JM1-32SC_BOOTMODEINSee 4 x 5 SoM Integration Guide and TEM0007 CPLD.
JM1-89JTAGSELINSee 4 x 5 SoM Integration Guide and TEM0007 CPLD.
JM2-18SC_nRSTINSee 4 x 5 SoM Integration Guide and TEM0007 CPLD.
JM2-93 / JM2-95 / JM2-97 / JM2-99TMS / TDI / TDO / TCKSignal-dependent

JTAG configuration and debugging interface.

JTAG reference voltage: 3.3VIN

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

  • Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

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List of all power rails which are accessible by the customer

  • Main Power Rails and Variable Bank Power


Scroll Title
anchorTable_PWR_PR
title-alignmentcenter
titleModule power rails.

Scroll Table Layout
orientationportrait
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repeatTableHeadersdefault
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cellHighlightingtrue


Power Rail Name/ Schematic NameConnector + PinDirection1)Notes
VINJM1.1 / JM1.3 / JM1.5 / JM2.2 / JM2.4 / JM2.6 / JM2.8INSupply voltage from the carrier board
3.3VINJM1.13 / JM1.15INSupply voltage from the carrier board
3.3VINJM2.91OUTJTAG reference voltage

+1.8V

JM1.39OUTInternal +1.8V voltage level

VCCIOB

JM2.1 / JM2.3INGeneral purpose I/O bank voltage

VCCIOD

JM2.7 / JM2.9INHigh speed I/O bank voltage (max. +1.8 V)

+3.3V

JM2.10 / JM2.12OUTInternal +3.3 V voltage level

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.

Scroll Title
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titleBaseboard Design Hints

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SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes
0---Configuration signal setup.See Configuration and System Control Signals.
13.3VIN3.3 V (± 5 %)-Management and SoC power supply.Main module power supply for management and SoC. 3 A recommended. Power consumption depends mainly on design and cooling solution.
2VIN3.3 V (± 5 %) 1)-Main module power supply.Main module power supply for management and SoC. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
3+1.8V--1.8 V on-module power supply.
4

VCCIOB / VCCIOD

2)-Module bank voltages.Enable bank voltages after 1.8 V are available on carrier.

1) A higher or lower input voltage may be possible. 

2) See DS0147 for additional information.

Board to Board Connectors

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    6 x 6 SoM LSHM B2B Connectors
    6 x 6 SoM LSHM B2B Connectors

Include Page
4 x 5 SoM LSHM B2B Connectors
4 x 5 SoM LSHM B2B Connectors

Technical Specifications

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List of all power rails which are accessible by the customer

  • Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings *)

Scroll Title
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titleAbsolute maximum ratings

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Power Rail Name/ Schematic NameDescriptionMinMaxUnit
VINSupply voltage-0.36.0V
3.3VINSupply voltage-0.33.75V

VCCIOB

I/O bank voltage-0.53.6V
VCCIODI/O bank voltage-0.52.0V


*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
   or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version.  Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

  • Variants of modules are described here: Article Number Information
  • Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
  • Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
  • Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
  • The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.


Scroll Title
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titleRecommended operating conditions.

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ParameterMinMaxUnitsReference Document
VIN3.1353.465V
3.3VIN3.1353.465V

VCCIOB

1.143.465VSee FPGA datasheet.
VCCIOD1.141.89VSee FPGA datasheet.

1) Higher and lower values may be possible. For more information consult schematic and according datasheets.

Physical Dimensions

  • Module size: 40 mm × 50 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm.

PCB thickness: 1.74 mm.

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guideline" .


Scroll Title
anchorFigure_TS_PD
title-alignmentcenter
titlePhysical Dimension


Scroll Ignore

draw.io Diagram
bordertrue
diagramNameTEM0007_TS_PD
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diagramWidth889
revision2


Scroll Only
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Currently Offered Variants 

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

    DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Scroll Title
anchorTable_VCP_SO
title-alignmentcenter
titleTrenz Electronic Shop Overview

Scroll Table Layout
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cellHighlightingtrue

Trenz shop TEM0007 overview page
English pageGerman page


Revision History

Hardware Revision History

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Set correct links to download  Carrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD
  • Example: 

    DateRevisionChangesDocumentation Link
    2020-11-25REV02
    • Resistors R14 and R15 was replaced by 953R (was 5K1)
    • Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
    REV02


Scroll Title
anchorFigure_RV_HRN
title-alignmentcenter
titleBoard hardware revision number.


Scroll Ignore

draw.io Diagram
top
bordertrue
diagramNameFigure_RV_HRN
simpleViewerfalse
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linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth269
revision1


Scroll Only


Scroll Title
anchorTable_RH_HRH
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titleHardware Revision History

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DateRevisionChangesDocumentation Link
2020-05-2601Inital ReleaseTEM0007-01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports
Scroll Title
anchorTable_RH_DCH
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titleDocument change history.

Scroll Table Layout
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repeatTableHeadersdefault
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cellHighlightingtrue

DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

Page info
infoTypeModified by
typeFlat
showVersionsfalse

Link fixed

2023-11-07

v.45

ED

Initial Release

--

all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --


Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices


Scroll Only


HTML
<style>
.wiki-content .columnLayout .cell.aside {
width: 0%;
}</style>



Scroll pdf ignore


Custom_fix_page_content

Table of contents

Table of Contents
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