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| Scroll pdf title |
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| title | On-board power rails summary. |
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power-rail
name | nominal
voltage (V) | maximum
current (A) | power
source | system
supply | user
supply |
|---|
Vb2b | 4.0 to 7.0 | 4.0 (4 pin × 1.0 A/pin) | JM5 | module | - |
|---|
Vusb | 5.0 | 0.5 | J1 | module | - |
|---|
Vsup | 4.0 to 7.0 | < 0.5 | Vusb | 3 × DC/DC DC/DC sync power-fail | JM5 (≤1.0 A) |
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< 4 | Vb2b | 3.3V | 3.3 | 3.0 | Vsup â–º DC/DC | module | JM4 (≤1.0 A) JM5 (≤1.0 A) |
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2.5V | 2.5 | 3.0 | Vsup â–º DC/DC | DDR SDRAM | JM5 (≤1.0 A) |
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1.2V | 1.2 | 3.0 | Vsup â–º DC/DC | VCCINT | JM5 (≤1.0 A) |
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VCCAUX | 2.5 | 0.3 | 3.3V â–º LDO | VCCAUX | JM4 (≤1.0 A) |
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3.3 | < 3.0 | 3.3V | VCCCIO0 | 2.5 | < 3.0 | 2.5V | VCCO
(bank 0) | JM4 (≤1.0 A) |
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3.3 | < 3.0 | 3.3V | JM4 (≤1.0 A) | 1.10 to 3.60 | 2.0 (2 pin × 1.0 A/pin) | JM4 (30 + 44) | JM4 (30 / 44) | |
If resistors R9 and R11 are populated and R12 is not populated, then TE0320 is power supplied through JM5 (B2B connector).
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| title | Power-on reset with fixed delay time of 200 ms |
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 Image Modified |
After this delay, the /RESET line is reset high and the FPGA configuration can start.
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| title | Reset assertion on power drop with fixed delay time of 200 ms. |
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| Image Modified |
Power-on Reset
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