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          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
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The Trenz Electronic TE0701 Carrier Board is a baseboard for 4 x 5 SoMs, which exposes the module's B2B connector pins to accessible connectors and provides a whole range of on-board components to test and evaluate TE 4 x 5 SoMs.

See page "4 x 5 cm carriers" to get information about the SoMs supported by the TE0701 carrier board.

Refer to http://trenz.org/te0701-info for the current online version of this manual and other available documentation.

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Scroll Title
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titleTE0701-06 block diagram


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TE0701 block diagram
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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below

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Scroll Title
anchorFigure_OV_MC
titleTE0701-06 main components


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  1. HDMI connector (1.4 HEAC support), J4
  2. Micro-USB2 connector, J12

  3. Pmod connector, J5

  4. Pmod connector, J6
  5. User push-button ("RESTART" button by default), S2
  6. User push-button ("RESET" button by default), S1
  7. 8x red user LEDs, D1 ... D8
  8. Mini-USB2 connector, J7
  9. User 4-bit DIP switch, S3
  10. VITA 57.1 compliant LPC FMC connector, J10
  11. Barrel jack for 12V power supply, J13
  12. ARM JTAG connector (DS-5 D-Stream), J15, functionality depends on module
  13. User 4-bit DIP switch, S4
  14. Pmod connector, J1
  15. RJ45 Gigabit Ethernet connector, J14
  16. SD Card connector, J8
  17. Pmod connector, J2
  18. Jumper, J18
  19. Mini CameraLink connector, J3
  20. CR1220 Backup-Battery holder, B1
  21. Trenz Electronic 4 x 5 modules B2B connectors, JB1 ... JB3
  22. Jumper J16, J17, J21
  23. Jumper J9, J19, J20
  24. Analog Devices ADV7511 HDMI Transmitter, U1
  25. Lattice Semiconductor MachXO2 1200 HC System Controller CPLD, U14
  26. FTDI FT2232H USB2 to JTAG/UART Bridge, U3

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Scroll Title
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titleInitial delivery state of programmable devices on the board

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Storage device name

Content

Notes

FTDI chip configuration EEPROM U9 (ST M93C66)

Xilinx License

Do not overwrite, see warning in related section
System Controller CPLD U14SC CPLD Firmware-


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Scroll Title
anchorTable_OV_CS
titleTE0701 Control Signals

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Control signal

Switch / Button / LED / PinSignal Schematic Names

Connected to

Functionality

Notes
SC CPLD JTAG EnableDIP switch S3-3JTAGENSC CPLD U14, pin 82

ON: SC CPLD JTAG enabled,
OFF: FPGA JTAG enabled

-
BOOT MODESC CPLD U14, pin 27MODEB2B JB1, pin 31Boot Mode for attached module (Flash or SD)-
Module ResetSC CPLD U14, pin 13RESINB2B JB2, pin 17Module Reset-
Global Reset inputPush Button S2S2SC CPLD U14, pin 2Manual reset from user-
SD Card detectionSD Slot J8, pin 10SD_DETECTSC CPLD U14, pin 40Detection Signal for inserted SD CardBoot mode is set to SD Boot,
when SD Card is detected.
Board status indicatorsRed LEDs D1 ... D8ULED1 ... ULED8SC CPLD U14, pins
78, 77, 76, 16, 69, 68, 65, 64		indicating various board and
module status / configuration		Refer to the firmware documentation of the SC CPLD
U14 and to the subsection 'LEDs' in section 'On-board Peripherals'
for more details and current functionality.
Board 3.3V power indicatorGreen LED D223V3INB2B JB1, pin 14, 16

ON: 3.3V on-board voltage available

-
FMC_VADJ voltage selectionDIP switches S4-1, S4-2, S4-3VID0 ... VID2SC CPLD U14, pins 34, 35, 38sets adjustable voltage for FMC connector-
I²C control / FMC_VADJ voltage selectionDIP switches S3-2, S3-1CM0, CM1SC CPLD U14, pins 99, 1enabling / disabling I²C control of board functionalities,
sets FMC_VADJ voltage (only 3 steps),
available to user if FMC_VADJ set by DIP-switch S4		Refer to the firmware documentation of the SC CPLD
U14 and and to the subsection 'DIP switches' in section 'On-board
Peripherals' for current functionality and more details.


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Notes:

  • For carrier or stand-alone boards use subsection for every connector typ (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

FMC LPC Connector

I/O signals and interfaces connected to the FPGA SoCs I/O bank and FMC connector J10:

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titleFMC connector J10 interface

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FMC Connector J2 Pins and InterfacesI/O Signal CountLVDS-pairs countConnected toVCCIO voltageNotes
I/O3417B2B JB1 connectorFMC_VADJ / 3V3_FMCpins usable as single ended I/O's and LVDS pairs
3417B2B JB2 connectorFMC_VADJ / 3V3_FMC
I²C2-SC CPLD U14, pin 8, 10-FMC I²C Geographical Address pins GA0 and GA1 set to GND.
JTAG4-SC CPLD U14, pin 4, 7, 9, 123.3V-
Clock Input-2B2B JB1 connector-2x bidirectional reference clock inputs
Control Signals2-SC CPLD U14, pin 20, 28-

'PG_C2M',  'FMC_PRSNT'

Reference voltage (FMC_VREF)1-B2B JB1 connector, pin 85, 97
B2B JB2 connector, pin 37, 93		-FMC sets thresholds of attached module's reference voltage (VREF pins).


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Scroll Title
anchorTable_SIP_ARM_JTAG
titleARM JTAG connector signals and pins

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Connector J15 pin
Schematic NameConnected toNotes

1, VTREF

FMC_VADJDCDC U18Voltage Target Reference
2, not connected---
3, NTRSTX0B2B JB1, pin 32active low Test Reset

4, GND

---
5, TDIX1B2B JB1, pin 34Test Data In
6, GND--

-

7, TMS / SWDIOX2B2B JB1, pin 36Test Mode Select
8, GND---
9, TCK / SWCLKX3B2B JB1, pin 38Test Clock
10, GND---

11, RTCK

X4B2B JB1, pin 42Return Test Clock
12, GND---
13, TDO / SWOX5B2B JB1, pin 44Test Data Out
14, not connected---
15, sRSTX6B2B JB1, pin 99active low System Test Reset
16, not connected---
17, not connected---
18, GND---
19, not connected---
20, GND---


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anchorFigure_SIP_JTAG/UART
titleJTAG/UART interface


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Micro-USB2 Connector

The TE0701 carrier board can be configured as a USB host. Hence, it must provide from 5.25V to 4.75V to the board side of the downstream connection (micro-USB port on J12). To provide sufficient power, a TPS2051 power distribution switch is located on the carrier board in between the 5V power supply and the VBUS signal of the USB downstream port interface. If the output load exceeds the current-limit threshold, the TPS2051 limits the output current and pulls the over-current logic output (OC_n) low, which is routed to the on-board CPLD. The TPS2051 is put into operation by setting J19 CLOSED. J20 provides an extra 200µF decoupling capacitor (in addition to 10µF) to further stabilize the output signal. Moreover, a series terminating resistor of either 1K 10K (J9:  1-2, 3) or 10K 1K (J9: 1, 2-3) is selectable on the "USB-VBUS" signal. Both signals, USB-VBUS and VBUS_V_EN (that enables the TPS2051 on "high") are routed (as well as the corresponding D+/- data lines) via the on-board connector directly to the USB 2.0 high-speed transceiver PHY of the mounted SoM. In summary, the default jumper settings are the following: J9: 1-2, 3 (1K 10K series terminating resistor); J19: CLOSED (TPS2051 in operation); J20: CLOSED (200 µF added).

Scroll Title
anchorFigure_SIP_MicroUSB2
titleTE0701 MicroUSB2 interface configuration


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MMC/SD-Card Socket

MMC/SD-Card socket is not directly wired to the B2B connector pins, but through a Texas Instruments TXS02612 SDIO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and MIO-bank of the Xilinx Zynq module. The Micro SD Card has 3.3V signal voltage level, but the MIO-bank on the Xilinx Zynq module has VCCIO of 1.8V.

...

Scroll Title
anchorTable_SIP_SD/MMC
titleSD/MMC Card socket signals and pins

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Connector J8 pinSignal Schematic NameMuxed to signal on Port ExpanderConnected toNotes
1, DAT3

DAT3/CS

SD_DAT3B2B JB1, pin 18-

2, CMD

CMD/MOSI

SD_CMD

B2B JB1, pin 26-

5, CLK

S_CLK

SD_CLK

B2B JB1, pin 28-

7, DAT0

DAT0/MISO

SD_DAT0

B2B JB1, pin 24-

8, DAT1

DAT1

SD_DAT1

B2B JB1, pin 22-

9, DAT2

DAT2

SD_DAT2

B2B JB1, pin 20-

10, CD

SD_DETECT

-SC CPLD U14, pin 40Card Detect

11, WP

SD_WP

-SC CPLD U14, pin 41Write Protect


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Scroll Title
anchorTable_SIP_RJ45
titleRJ45 Ethernet MegJack MagJack signals and pins

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RJ45 MegJack MagJack J14 pinSignal Schematic NameConnected toNotes
LED1PHY_LED1SC CPLD U14, pin 42Yellow
LED2PHY_LED2SC CPLD U14, pin 43Green
PHY_MDIPHY_MDI0_PB2B JB1, pin 3-
PHY_MDI0_NB2B JB1, pin 5-
PHY_MDI1_PB2B JB1, pin 9-
PHY_MDI1_NB2B JB1, pin 11-
PHY_MDI2_PB2B JB1, pin 15-
PHY_MDI2_NB2B JB1, pin 17-
PHY_MDI3_PB2B JB1, pin 21-
PHY_MDI3_NB2B JB1, pin 23-


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Scroll Title
anchorTable_SIP_CL
titleMini CameraLink singals and pins

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CameraLink J3 pinSignal Schematic NameConnected toNotes
Pin 20, 7CL_TC_P / CL_TC_NB2B JB2, Pin 12, 14Communication lanes
Pin 6, 19CL_TFG_P / CL_TFG_N

B2B JB2, Pin 16, 18

Pin 9, 22CL_CLK_P / CL_CLK_NB2B JB3, Pin 31, 33Data clock
Pin 18, 5CL_CC1_P / CL_CC1_NB2B JB3, Pin 26, 28Control lanes
Pin 17, 4CL_CC2_P / CL_CC2_NB2B JB3, Pin 20, 22
Pin 16, 3CL_CC3_P / CL_CC3_NB2B JB3, Pin 14, 16
Pin 15, 2CL_CC4_P / CL_CC4_NB2B JB3, Pin 8, 10
Pin 12, 25CL_X0_P / CL_X0_NB2B JB3, Pin 25, 27Data lanes
Pin 11, 24CL_X1_P / CL_X1_NB2B JB3, Pin 19, 21

Pin 10, 23

CL_X2_P / CL_X2_NB2B JB3, Pin 13, 15
Pin 8, 21CL_X3_P / CL_X3_NB2B JB3, Pin 7, 9
Pin 1, 2312V0_CL12V Main Power supply (12V_LC)filtered and protected supply voltage


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Scroll Title
anchorTable_SIP_HDMI
titleHDMI connector signals and pins

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HDMI connector J4 pinSignal Schematic NameConnected toNotes
Pin 1, 3HDMI_TX2_P / HDMI_TX2_NHDMI transmitter, Pin 43, 42also connected to HDMI protection circuit
Pin 4, 6HDMI_TX1_P / HDMI_TX1_N

HDMI transmitter, Pin 40, 29

also connected to HDMI protection circuit

Pin 7, 9HDMI_TX0_P / HDMI_TX0_NHDMI transmitter, Pin 36, 35also connected to HDMI protection circuit
Pin 10, 12HDMI_TXC_P / HDMI_TXC_NHDMI transmitter, Pin 33, 32also connected to HDMI protection circuit
Pin 13CEC_BHDMI transmitter, Pin 48HDMI CEC, wired through HDMI protection circuit
Pin 15SCL_BHDMI transmitter, Pin 53HDMI I²C clock line, wired through HDMI protection circuit
Pin 16SDA_BHDMI transmitter, Pin 54HDMI I²C data line, wired through HDMI protection circuit
Pin 19HPD_BHDMI transmitter, Pin 30Hot Plug Detect, wired through HDMI protection circuit
Pin 185V_HDMIHDMI protection circuit, Pin 135V supply voltage, wired through HDMI protection circuit


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anchorTable_SIP_Pmod
titlePmod connectors pin description

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Pmod connector J1 pinSignal Schematic NameConnected toNotes
1MIO0B2B connector JB1, pin 88; DIP switch S3-4-
2MIO9B2B connector JB1, pin 92-
3MIO14B2B connector JB1, pin 91; SC CPLD U14, pin 37-
4MIO15B2B connector JB1, pin 86; SC CPLD U14, pin 18-
7MIO13B2B connector JB1, pin 98; SC CPLD U14, pin 30-
8MIO10B2B connector JB1, pin 96; SC CPLD U14, pin 29-
9MIO11B2B connector JB1, pin 94; SC CPLD U14, pin 19-
10MIO12B2B connector JB1, pin 100; SC CPLD U14, pin 36-
Pmod connector J2 pinSignal Schematic NameConnected toNotes
1PX3SDIO Port Expander U2, pin 10muxed to signal 'SD_DAT3' (B2B JB1, pin 18)
2PX4SDIO Port Expander U2, pin 12muxed to signal 'SD_CMD' (B2B JB1, pin 26)
3PX0SDIO Port Expander U2, pin 14muxed to signal 'SD_DAT0' (B2B JB1, pin 24)
4PX5SDIO Port Expander U2, pin 13muxed to signal 'SD_CLK' (B2B JB1, pin 28)
7PX1SDIO Port Expander U2, pin 15muxed to signal 'SD_DAT1' (B2B JB1, pin 22)
8PX2SDIO Port Expander U2, pin 8muxed to signal 'SD_DAT2' (B2B JB1, pin 20)
9PX6SC CPLD U14, pin 49-
10PX7SC CPLD U14, pin 48-
Pmod connector J5 pinSignal Schematic NameConnected toNotes
1PA1_PB2B connector JB2, pin 27usable as LVDS pair
2PA1_NB2B connector JB2, pin 25
3PA2_PB2B connector JB2, pin 26usable as LVDS pair
4PA2_NB2B connector JB2, pin 28
7PA0_PB2B connector JB2, pin 23usable as LVDS pair
8PA0_NB2B connector JB2, pin 21
9PA3_PB2B connector JB2, pin 22usable as LVDS pair
10PA3_NB2B connector JB2, pin 24
Pmod connector J6 pinSignal Schematic NameConnected toNotes
1PB2_NB2B connector JB2, pin 51usable as LVDS pair
2PB2_PB2B connector JB2, pin 53
3PB0_NB2B connector JB2, pin 33usable as LVDS pair
4PB0_PB2B connector JB2, pin 31
7PB3_NB2B connector JB2, pin 47usable as LVDS pair
8PB3_PB2B connector JB2, pin 45
9PB1_NB2B connector JB2, pin 43usable as LVDS pair
10PB1_PB2B connector JB2, pin 41


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anchorTable_OBP_SC_CPLD
titleSystem Controller CPLD I/O pins

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SC CPLD U14 Pins and InterfacesConnected toFunctionNotes
FMC_TMSFMC J10, pin D31FMC JTAG-
FMC_TDIFMC J10, pin D29
FMC_TDOFMC J10, pin D30
FMC_TCKFMC J10, pin D33
FMC_SDAFMC J10, pin C31FMC I²C-
FMC_SCLFMC J10, pin C30
PG_C2MFMC J10, pin D1FMC control signals-
FMC_PRSNTFMC J10, pin H2
EN_FMCDC-DC U18, Load switch Q1FMC power control signals-
POK_FMCDC-DC U18
S1Pushbutton S1available to user-
S2Pushbutton S2Global Reset in standard configuration-
M_TDOFTDI chip, pin 14 (ADBUS2)

SC CPLD JTAG interface activated
if DIP switch S3-3 in OFF-position.

Attached module JTAG interface activated if
DIP switch S3-3 in ON-position.

-
M_TDIFTDI chip, pin 13 (ADBUS1)
M_TCKFTDI chip, pin 12 (ADBUS0)
M_TMSFTDI chip, pin 15 (ADBUS3)
JTAGENDIP switch S3-3
C_TMSB2B JB2, pin 94

Forwarded JTAG signals from FTDI chip,
if DIP switch S3-3 in ON-position.

JTAG signals
buffered with
ICs U4, U6,U7, U8
C_TCKB2B JB2, pin 100
C_TDOB2B JB2, pin 98
C_TDIB2B JB2, pin 96
ADBUS4FTDI chip, pin 17FIFO / GPIO's available to user-
ADBUS7FTDI chip, pin 20
ACBUS4FTDI chip, pin 26
ACBUS5FTDI chip, pin 27
BDBUS0FTDI chip, pin 32UART TX from FTDI (forwarded to MIO14)UART signals connected
to attached module
BDBUS1FTDI chip, pin 33UART RX to FTDI (forwarded from MIO15)
EN1B2B JB1, pin 27SoM control signals, functionalities depend
also on attached SoM's SC CPLD firmware.		-
NOSEQB2B JB1, pin 8
PGOODB2B JB1, pin 29
RESINB2B JB2, pin 17
MODEB2B JB1, pin 31
ULED1SC CPLD U14, pin 78Red LED D1

USER LEDs, refer to the current firmware
documentation of the SC CPLD.

-
ULED2SC CPLD U14, pin 77Red LED D2
ULED3SC CPLD U14, pin 76Red LED D3
ULED4SC CPLD U14, pin 16Red LED D4
ULED5SC CPLD U14, pin 69Red LED D5
ULED6SC CPLD U14, pin 68Red LED D6
ULED7SC CPLD U14, pin 65Red LED D7
ULED8SC CPLD U14, pin 64Red LED D8
Y0B2B JB2, pin 42User I/O's between SC CPLD U14 and
attached module		-
Y1B2B JB2, pin 44
Y2B2B JB2, pin 90
Y3B2B JB2, pin 91
Y4B2B JB2, pin 99
Y5B2B JB2, pin 35
Y6B2B JB1, pin 87
X6B2B JB1, pin 99; ARM JTAG J15, pin 15ARM JTAG sRST (active low System Test Reset)-
PHY_LED1RJ45 connector J14Current indicating function depends on
SC CPLD firmware.		-
PHY_LED2
SEL_SDSDIO port expander U2Control signal to select Port B0 or B1.-
SD_DETECTSD/MMC Card socket J8, pin 10Card Detect signal-
SD_WPSD/MMC Card socket J8, pin 11Write Protect signal
HDMI_SCLHDMI Transmitter U1, pin 55HDMI transmitter 2-wire serial bus-
HDMI_SDAHDMI Transmitter U1, pin 56
HDMI_SPDIFOUTHDMI Transmitter U1, pin 46Unidirectional HDMI S/PDIF lines-
HDMI_SPDIFHDMI Transmitter U1, pin 10
CM0DIP switch S3-2

Set FMC_VADJ "S3-1 | S3-2: FMC_VADJ":

OFF | OFF :   1.8V
OFF | ON  :   2.5V
ON  | OFF :   2.2V
ON  | ON  :   I2C control enabled

DIP switch S4-1, S4-2 and S4-3
have to be set to OFF if use DIP
switches S3-1 and S3-2.

CM1DIP switch S3-1
CM2DIP switch S4-4depends on current SC CPLD firmware-
VID0DC-DC U18, pin 34; DIP switch S4-1set bit pattern as "VID2 | VID1 | VID0: FMC_VADJ":

0 | 0 | 0 :   3.3V
0 | 0 | 1 :   2.5V
0 | 1 | 0 :   1.8V
0 | 1 | 1 :   1.5V
1 | 0 | 0 :   1.25V
1 | 0 | 1 :   1.2V
1 | 1 | 0 :   0.8V (not supported as VCCIO standard)
1 | 1 | 1 :   Reserved

SC CPLD settings will
be overridden by DIP switch
S4, if one of them is set to
one (OFF-position).
VID1DC-DC U18, pin 33; DIP switch S4-2
VID2DC-DC U18, pin 32; DIP switch S4-3
USB_OCUSB-VBUS Load Switch U11, pin 5Indicates current threshold of USB devices exceeded.low active logic
MIO10B2B JB1, pin 96; Pmod J1, pin 8User I/O's between SC CPLD U14, attached module
and Pmod connector J1.		-
MIO11B2B JB1, pin 94; Pmod J1, pin 9
MIO12B2B JB1, pin 100; Pmod J1, pin 10
MIO13B2B JB1, pin 98; Pmod J1, pin 7
MIO14B2B JB1, pin 91; Pmod J1, pin 3UART interface in standard SC CPLD firmware, else
user I/O's.
MIO15B2B JB1, pin 86; Pmod J1, pin 4
PX6Pmod J2, pin 9User I/O's of SC CPLD U14-
PX7Pmod J2, pin 10
VCCIO03V3INVCCIO SC CPLD bank 0-
VCCIO1VIOTBVCCIO SC CPLD bank 1adjustable voltage, see section 'Power'
VCCIO23V3INVCCIO SC CPLD bank 2-
VCCIO33V3INVCCIO SC CPLD bank 3-


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anchorTable_OBP_ft2232
titleFT2232H interface connections

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FT2232H U3 PinSignal Schematic NameConnected toNotes
Pin 12, ADBUS0M_TCKSC CPLD U14, pin 91
JTAG interface
Pin 13, ADBUS1M_TDISC CPLD U14, pin 94
Pin 14, ADBUS2M_TDOSC CPLD U14, pin 95
Pin 15, ADBUS3M_TMS

SC CPLD U14, pin 90

Pin 20, ADBUS7ADBUS7SC CPLD U14, pin 97

UART and
user configurable

GPIO's
Pin 26, ACBUS4ACBUS4SC CPLD U14, pin 96
Pin 27, ACBUS5ACBUS5SC CPLD U14, pin 88
Pin 32, BDBUS0BDBUS0SC CPLD U14, pin 87
Pin 33, BDBUS1BDBUS1SC CPLD U14, pin 86
Pin 40, BDBUS7JTAGENDIP switch S3-3; SC CPLD U14, pin 82Control line


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anchorTable_OBP_SDIO_PortExpander
titleTI TXS02612 interface description

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TI TXS02612 U2 Port A Pins and SignalsConnected toTI TXS02612 U2 Port B0 and B1 Pins and SignalsConnected toNotes
Pin 6, 'SD_DAT0'B2B JB1, pin 24Pin 18, 'DAT0/MISO', Port B0SD/MMC Socket J8, pin 7

The SD IO port expander
connects the signals of Port A
to Port B0 or B1 depending
on the state of the control line

'SEL_SD' (pin 24), connected to SC CPLD
U14, pin 39.

When 'SEL_SD' is low, port B0 is selected,
when 'SEL_SD' is high, port B1 is selected.

Pin 14, 'PX0', Port B1Pmod J2, pin 3
Pin 7, 'SD_DAT1'B2B JB1, pin 22Pin 16, 'DAT1', Port B0SD/MMC Socket J8, pin 8
Pin 15, 'PX1', Port B1Pmod J2, pin 7
Pin 1, 'SD_DAT2'B2B JB1, pin 20Pin 23, 'DAT2', Port B0SD/MMC Socket J8, pin 9
Pin 8, 'PX2', Port B1Pmod J2, pin 8
Pin 3, 'SD_DAT3'B2B JB1, pin 18Pin 22, 'DAT3/CS', Port B0SD/MMC Socket J8, pin 1
Pin 10, 'PX3', Port B1Pmod J2, pin 1
Pin 4, 'SD_CMD'B2B JB1, pin 26Pin 20, 'CMD/MOSI', Port B0SD/MMC Socket J8, pin 2
Pin 12, 'PX4', Port B1Pmod J2, pin 2
Pin 9, 'SD_CLK'B2B JB1, pin 28Pin 19, 'SCLK', Port B0SD/MMC Socket J8, pin 5
Pin 13, 'PX5', Port B1Pmod J2, pin 4


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anchorTable_OBP_HDMI
titleHDMI transmitter signals and interface

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AD ADV7511KSTZ U1 Pins and SignalsConnected toProtection Circuit U10Notes
'HDMI_D0' ... 'HDMI_D11', Pin 85 ... 96B2B JB3--
'HDMI_TXC_N, HDMI_TXC_P, Pin 32, 33HDMI J4, pin 12, 10ESD protection-
'HDMI_TX0_N, HDMI_TX0_P, Pin 35, 36HDMI J4, pin 9, 7ESD protection-
'HDMI_TX1_N, HDMI_TX1_P, Pin 39, 40HDMI J4, pin 6, 4ESD protection-

'HDMI_TX2_N, HDMI_TX2_P, Pin 42, 43

HDMI J4, pin 3, 1ESD protection-
'HDMI_VS', Pin 2B2B JB3, pin 60--
'HDMI_HS', Pin 98B2B JB3, pin 58--
'HDMI_CLK', Pin 79B2B JB3, pin 59--
'HDMI_DE', Pin 97B2B JB3, pin 57--
'HPD_A', Pin 30HDMI J4, pin 19signal pass-thru level shifted signal ('HPD_B') to 5V
'CEC_A', Pin 48HDMI J4, pin 13signal pass-thru level shifted signal ('CEC_B') to 5V
'CEC_CLK', Pin 50B2B JB2, pin 38--
'SCL_A', Pin 53HDMI J4, pin 15signal pass-thru level shifted signal ('SCL_B') to 5V
'SDA_A', Pin 54HDMI J4, pin 16signal pass-thrulevel shifted signal ('SDA_B') to 5V
'HDMI_SCL', Pin 55B2B JB2, pin 13, SC CPLD U14, pin 47-I²C bus lines also used
for I2C control control (if activated) of
some other SC CPLD U14 functions
'HDMI_SDA', Pin 56B2B JB2, pin 15; SC CPLD U14, pin 45-
'HDMI_INT', Pin 45B2B JB2, pin 32--
'HDMI_SPDIF', Pin 10SC CPLD U14, pin 15--
'HDMI_SPDIFOUT', Pin 46SC CPLD U14, pin 14--
TPD12S016 U10 Control SignalsConnected toFunctionalityNotes
LS_OEB2B JB2, pin 36enable Level Shifter (1.8V ↔ 5.0V)Both signals must be
HIGH level for full functionality
of HDMI Protection Circuit U10.
CT_HPDB2B JB2, pin 34enable Load Switch for HPD


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titleDIP-switches functionality description

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DIP-switch S3Signal Schematic NameConnected toFunctionalityNotes
S3-1

CM1

SC CPLD U14, pin 1

Set FMC_VADJ "S3-1 | S3-2: FMC_VADJ":

OFF | OFF :   1.8V
OFF | ON  :   2.5V
ON  | OFF :   2.2V
ON  | ON  :   I2C control enable

DIP switch S4-1, S4-2 and S4-3
have to be set to OFF if use DIP
switches S3-1 and S3-2.

S3-2

CM0

SC CPLD U14, pin 99
S3-3

JTAGEN

SC CPLD U14, pin 82

Positions:
ON:  enables JTAG interface of module
OFF: enables JTAG interface of SC CPLD U14

JTAG interface accessible through FTDI chip with Mini-USB2 B
connector J7

S3-4

MIO0

Pmod J1, pin 1; B2B JB1, pin 88depends on attached module-
DIP-switch S4Signal Schematic NameConnected toFunctionalityNotes
S4-1VID0SC CPLD U14, pin 34set 3bit code to adjust FMC_VADJ voltage

The FMC_VADJ voltage is provided by DCDC U8 EN5335QI,

Set DIP-switches as bit pattern "S4-3 | S4-2 | S4-1:  FMC_VADJ":

ON  | ON  | ON  :   3.3V
ON  | ON  | OFF :   2.5V
ON  | OFF | ON  :   1.8V
ON  | OFF | OFF :   1.5V
OFF | ON  | ON  :   1.25V
OFF | ON  | OFF :   1.2V
OFF | OFF | ON  :   0.8V (not supported as VCCIO standard)
OFF | OFF | OFF :   activate I2C control of some SC CPLD functions

S4-2VID1SC CPLD U14, pin 35
S4-3VID2SC CPLD U14, pin 38
S4-4CM2SC CPLD U14, pin 51depends on current SC CPLD firmware-


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titleOn-board Push Buttons

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-
ButtonConnected toFunctionNotes
S1SC CPLD U14, pin 3User button, function depends on SC CPLD firmware.-
S2SC CPLD U14, pin 2Global Reset of board and attached module, as all power supplies
will be switched off on button push and back on again on button release.		-


Note: Functionality depends also on CPLD Firmware: TE0701 CPLD

On-board LEDs

The TE0701 board is equipped with several LEDs to indicate states and activities.

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titleOn-board LEDs description

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LED ColorConnected toDescription and Notes
D22green3.3VINindicates available 3.3V voltage level of attached module
D1redSC CPLD U14, pin 78

functionality depends on the current firmware of the SC CPLD,
refer to the documentation.

D2redSC CPLD U14, pin 77
D3redSC CPLD U14, pin 76
D4redSC CPLD U14, pin 16
D5redSC CPLD U14, pin 69
D6redSC CPLD U14, pin 68
D7redSC CPLD U14, pin 65
D8redSC CPLD U14, pin 64


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titleOn-board oscillators

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Clock SourceSignal Schematic NameFrequencyClock Input Destination
SiTime SiT8008AI oscillator, U20

OSCI

12.000000 MHzUSB2 to JTAG/UART adapter U3, pin 3


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anchorFigure_PWR_PD
titlePower Distribution


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Power-On Sequence

The on-board voltages 3.3V and 5.0V of the carrier board will be powered up simultaneously when 12V power supply is connected to the barrel jack J10.

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titlePower Sequency


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Configuring mounted SoM's PL bank VCCO FMC_VADJ

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titleConfiguring FMC_VADJ

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 S4-1S4-2S4-3

FMC_VADJ Value

ONONON3.3V
OFFONON2.5V
ONOFFON1.8V
OFFOFFON1.5V
ONONOFF1.25V
OFFOFFOFFAttention: Set VADJ to S3-M1 and S3-M2 control, read TE0701 System Controller CPLD description, before this mode is used!


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There are two baseboard supply voltages VIOTA and VIOTB connected to the 4 x 5 SoM's PL IO-bank. The supply-voltages have following pin assignments on B2B-connectors:

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titleBaseboard supply-voltages VIOTA and VIOTB

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Baseboard supply voltages

TE0701 B2B connector-pins

Standard 4 x 5 SoM's VCCO pins on B2B connectors

Connected with (Pull-up, VCCIO)

VIOTAJB2-2, JB2-4, JB2-6VCCIOB (JM2-1, JM2-3) / VCCIOC (JM2-5)HDMI_SCL, HDMI_SDA, HDMI_INT, J5 VCCIO
VIOTBJB1-10, JB1-12, JB2-8, JB2-10VCCIOA (JM1-9, JM1-11) / VCCIOD (JM2-7, JM2-9)VCCIO1 (System Controller CPLD pin 55, 73)


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titleConfiguration of baseboard supply-voltages via jumpers

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Voltage Levels

VIOTAVIOTBUSB-VBUS12V0_CL
3V3J17:1-2, 3 & J16: openJ17: 1-2, 3 & J16: open & J21:1-2, 3--
2V5J17:1, 2-3 & J16: openJ17:1, 2-3 & J16: open & J21: 1-2, 3--
FMC_VADJJ17: open & J16: 1-2J21:1, 2-3--
5V0 intern--

J9:1-2, 3 & J19: 1-2

(J20: 1-2: additional decoupling-capacitor 200 µF)

-
VBUS extern--J9: 1, 2-3 & J19: open-
12V_LC---J18: 1-2


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titlePower pin description of B2B Module Connector

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Module Connector (B2B) DesignatorVCC / VCCIODirectionPinsNotes
JB1

5V0

Out

2, 4, 6

5.0V module supply voltage
3.3VINOut14, 163.3V module supply voltage
VIOTBOut10, 12PL IO-bank VCCO
VIOBIn401.8V module output voltage
JB2

3.3VOUT

In

9, 11

3.3V module output voltage
5V0Out1, 3, 5, 75.0V module supply voltage
VIOTAOut2, 4, 6PL IO-bank VCCO
VIOTBOut8, 10PL IO-bank VCCO
VCCJTAGIn923.3V JTAG reference voltage
JB3USB-VBUSOut56USB Host supply voltage


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titlePower pin description of FMC connector

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FMC DesignatorVCC / VCCIODirectionPinsNotes
J10

12V_LC

In

Pin C35, C37

-
3V3_FMCInPin D36, D38, D40, C39-
3.3VOUTInPin D32-
FMC_VADJOutPin G39, H40adjustable FMC VCCIO


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titlePower pin description of Pmod connectors

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PMOD DesignatorVCC / VCCIODirectionPinsNotes
J13.3VOUTOutPin 6, 12-
J23.3VOUTOutPin 6, 12-
J5VIOTAOutPin 6, 12-
J6FMC_VADJOutPin 6, 12-


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titlePower pin description of main power supply connectors

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Main Power Jack DesignatorVCC / VCCIODirectionPinsNotes
J1312VINIn

1

-
B1VBATIn+CR1220 Battery Holder (3.0V)


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titlePower pin description of peripherals' connectors

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Peripheral Socket DesignatorVCC / VCCIODirectionPinsNotes
J15FMC_VADJIn1ARM JTAG reference voltage VTREF
J312V0_CLIn1, 2612V CameraLink power supply voltaghe
J7VBUSIn1USB2.0 device mode USB VBUS
J45V_HDMIOut185V HDMI supply voltage from HDMI Protection Circuit U10
J83.3VOUTOut4MicroSD Card Socket
J12USB-VBUSIn / Out1Direction depends on USB2 mode (OTG, Host, Device mode)


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titlePower Pin description of VCCIO selection jumpers

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Jumper / Header DesignatorVCC / VCCIODirectionPinsNotes
J17VIOTAIn2-
3.3VVOUTOut1-
2V5Out3-
J21

VIOTA

In1-
VIOTBIn2-
FMC_VADJOut3-
J16FMC_VADJOut2-
VIOTAIn1-
J1812V_LCOut1-
12V0_CLIn2-
J6VCCIOCIn2, 4, 6-
M1.8VOUTOut1-
J9USB-VBUSIn2-
VBUSOut31K13 serial resistor
VBUSOut110K serial resistor
J195.0VOut15.0V from USB-VBUS load switch U11
VBUSIn2-
J205.0VIn1USB-VBUS voltage stabilization with
additional 200µF capacitance.
5.0VOut2


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titleModule absolute maximum ratings

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ParameterMinMaxUnitsNotes

VIN supply voltage

11.4

12.6

V

ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) standard
I/O input voltage for SC CPLD U114-0.53.75VLattice MachXO2 Family datasheet
Voltage on TXS02612RTWR pins-0.53.8VTI  TXS02612RTWR data sheet

Storage temperature

-40100

°C

LED's SML-P11MTT86 data sheet


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titleRecommended Operating Conditions

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 ParameterMinMaxUnitsNotes
VIN supply voltage11.412.6V-
I/O input voltage for SC CPLD U14-0.33.6VLattice MachXO2 Family datasheet
Voltage on TXS02612RTWR pins03.3VTI  TXS02612RTWR data sheet

Operating Temperature Range 1), 2), 3)

-4008570°C-



1) Temperature range may vary depending on assembly options

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titleTrenz Electronic Shop Overview

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Trenz shop TE0701 overview page
English pageGerman page


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titleHardware Revision History

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DateRevision

Notes

PCNDocumentation link
-06

Additional Jumper J16 and switch S4
for setting voltage FMC_VADJ.

PCN-20161128

TE0701-06

-05Improved manufacturing-TE0701-05
-04--TE0701-04
-03Changed DC/DC converters-TE0701-03
-02Prototype-TE0701-02
-

01

Prototype

-TE0701-01


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titleDocument change history

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DateRevisionAuthorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse



Page info
infoTypeModified by
typeFlat
showVersionsfalse

  • Corrected USB J9 description
  • Typos
  • update Button description
  • Note for J15

2019-01-11

v.73
John Hartfiel
  • correction temperature range

2018-10-22

v.72Ali Naseri
  • General TRM revision and updated to new style
2018-06-13


v.66

Ali Naseri
  • updated Power-on sequence diagram
2018-01-12

v.62

John Hartfiel
  • Dual PMOD note
2017-11-09v.60John Hartfiel
  • add B2B connector section
2017-08-15

v.59

John Hartfiel
  • Add VCCIO Jumper Pin location.
  • Updated VADJ description.
2017-08-14v.58John Hartfiel
  • Description correction.
2017-05-25v.56Jan Kumann
  • New physical dimensions drawing of the board.
2017-05-16

v.51

Jan Kumann
  • A few overall improvements and corrections, new  block diagram.
2017-04-11


Ali Naseri
  • added block diagram
2017-02-15

v.45

Ali Naseri
  • added warning concerning the use of FTDI tools
2017-02-15v.40Ali Naseri
  • added power-on sequence diagram
2017-01-19

v.35

Ali Naseri
  • correction of table 3 (switch-positions to adjust FMC_VADJ)
  • inserted hint to set and measure the PL IO-bank supply-voltages
2017-01-13

v.20

Ali Naseri
  • added section for baseboard supply voltage configuration
2016-11-29
v.10


Ali Naseri
  • TRM update due to new revision 06 of
  • the carrier board.
2016-11-28v.4

Ali Naseri

  • TRM adjustment to the newest
  • revision (05) of TE0701 Carrier Board.
2014-02-18
0.2
Sven-Ole Voigt
  • TE0701-03 (REV3) updated
2014-01-05

0.1

Sven-Ole Voigt
  • Initial release


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