Page History
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| Name / opt. VHD Name | Direction | Pin | Description | |
|---|---|---|---|---|
| JTAGEN | in | 26 | Switch JTAG between CPLD and FPGA (logical one for CPLD, logical zero for FPGA) | |
| TMS / M_TMS | IN | 29 | JTAG from B2B connector | |
| TCK / M_TCK | IN | 30 | JTAG from B2B connector | |
| TDI / M_TDI | IN | 32 | JTAG from B2B connector | |
| TDO / M_TDO | OUT | 1 | JTAG from B2B connector | |
| F_TMS / C_TMS | OUT | 21 | JTAG to FPGA | |
| F_TCK / C_TCK | OUT | 17 | JTAG to FPGA | |
| F_TDI / C_TDI | OUT | 23 | JTAG to FPGA | |
| F_TDO / C_TDO | IN | 20 | JTAG to FPGA | |
| ULI_SYSTEM / XIO | IN | 4 | FPGA access W22 PIN | |
| FPGA_IO | INOUT | 10 | FPGA access U22 PIN (PUDC) | |
| RESIN | IN | 16 | RESETIN from B2B connector (Negative Reset) | |
| DONE | IN | 28 | FPGA Configuration DONE_0 Pin | |
| PROG_B | OUT | 27 | FPGA Configuration PROGRAM_B_0 Pin | |
| PGOOD | OUT | 12 | PGOOD to B2B connector | |
| 3.3V / PG_SENSE | IN | 25 | from module generated 3.3V Voltage | |
| EN1 | IN | 11 | Power Enable from B2B Connector (Positive Enable) | |
| SYSLED2 / LED1 | OUT | 8 | Module LED D2 (Red) | |
| SYSLED1/ LED2 | OUT | 9 | Module LED D1 (Green) | |
| MODE | 13 | / currently_not_used | ||
| NOSEQ | 14 | / currently_not_used | ||
| ULI_CPLD | 5 | / currently_not_used |
Functional Description
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PGOOD is zero, if EN1 or PG_SENSE is zero else high impedance state.
PUDC is high during FPGA power up.
FPGA Configuration
FPGA configuration process will be stared, if RESIN, PG_SENSE and EN1 is ONE.
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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| REV01 | REV01, REV02 | | document
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| 2017-01-26 | v.17 | REV01 | REV01, REV02 |
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| 2016-11-04 | v.1 | --- |
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| All |
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Appx. B: Legal Notices
| Include Page | ||||
|---|---|---|---|---|
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Overview
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