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Used only for CPLD Firmwareupdate. Second chip in JTAG chain when switch S3:2 is ON.
RESET
Name | Description |
---|---|
SSD1_PERSTn | SC_IO0 |
ETH_RST | Slow Reset from SC_IO0 |
USB0_RST | Slow Reset from SC_IO0 |
USBH_RST | Slow Reset from SC_IO0 |
PLL_RST | Slow Reset from SC_IO0 |
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LEDs
LED | Value | Description |
---|---|---|
XMOD1_E | Counter Bit or XMOD1_G | |
LED1_1A | not PHY_LED1 | Yellow LED is PHY RX Indicator (with default PHY settings) |
LED_2A | not PHY_LED0 | Green LED is PHY LINK Indicator (with default PHY settings) |
LED_2B | 0 | Stub to use only green from dual Green/Orange LED |
LED1 | DP_TX_HPD | DisplayPort Hotplug Detection |
LED2 | hub_rst_n | USB hub reset indicator |
LED3 | SSD1_LED | LED output from M2 slot |
LED4 | F1_SENSE | |
SFP_LED1 | 0 | |
SFP_LED2 | 0 | |
SFP_LED3 | 0 | |
SFP_LED4 | 0 |
UART
Output | Input |
---|---|
MIO42 | XMOD1_B |
XMOD1_A | MIO43 |
Display Port
Output | Input |
---|---|
DP_AUX_TX | B66_T1 |
DP_AUX_DE | not B66_T2 |
B66_T3 | DP_AUX_RX |
B67_T1 | DP_TX_HPD |
SD
SD_EN is "0". Enable power for SD slot.
SFP
All Transmit for all SFP is enabled.
USB
USB Mode pins constant "11" (default boot mode).
SSD
SSD1_WAKE is "0".
Anchor | ||||
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I2C Baseaddress: 0x74. I2C with 8Bit Register Address with 8Bit Data. I2C CLK currently 100 MHz supported.
Write access
Register Address | Name | Description |
---|---|---|
0 | FAN CTRL | Enable FAN, Bit 0-2 Fan1 to Fan2, Default all 1 |
1 | FAN1 |
PWM | FAN1 PWM (0%-100%, Default 30%) |
2 | FAN2 |
PWM | FAN2 PWM (0%-100%, Default 30%) |
3 | FAN3 |
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PWM | FAN3 PWM (0%-100%, Default 30%) |
Read access
Register Address | Name | Description |
---|---|---|
0 | FAN CTRL | FAN Control register |
1 | FAN1 RPS | FAN1 Revolutions per second |
2 | FAN2 RPS | FAN2 Revolutions per second |
3 | FAN3 RPS | FAN3 Revolutions per second |
FANs
PLL
PLL Selection pins constant "00".
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Overview
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