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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware



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Table of contents

Table of Contents
outlinetrue

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Name / opt. VHD NameDirectionPinDescription
ACBUS4                96FTDI / currently_not_used
ACBUS5                88FTDI / currently_not_used
ADBUS4               out98constant 0 / currently_not_used
ADBUS7               in97/ currently_not_used
BDBUS0               in87UART TX from FTDI
BDBUS1               out86UART RX to FTDI
C_TCKout81JTAG FTDI
C_TDIout84JTAG FTDI
C_TDOin83JTAG FTDI
C_TMSout85JTAG FTDI
CM0                  in99DIP Switch S3-M1
CM1                  in1DIP Switch S3-M2

CM2

in51REV06+ only: DIP Switch S4-1 4 / RGPIO Bus (powered by VIOTB (FMC VADJ))
EN_FMC               out31VADJ and 3V3V_FMC Power on
EN1                  out24Power Enable Pin for Module CPLD
FMC_PRSNT            in28FMC Card present pin (zero if not present)
FMC_SCL              out10FMC I2C
FMC_SDAinout8FMC I2C
FMC_TCK              out4JTAG FMC / currently_not_used
FMC_TDI              out12JTAG FMC / currently_not_used
FMC_TDO              in9JTAG FMC / currently_not_used
FMC_TMS              out7JTAG FMC / currently_not_used
HDMI_SCL             inout47HDMI / used also for I2C FMC control
HDMI_SDA             inout45HDMI / used also for I2C FMC control
HDMI_SPDIF           out15HDMI / currently_not_used
HDMI_SPDIFOUT        in14HDMI / currently_not_used
JTAGEN               --82

Enable JTAG access to carrier CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)

Set DIP Switch S3-JTAGEN to ON, for module access.

M_TCK                in91JTAG Module
M_TDI                in94JTAG Module
M_TDO                out95JTAG Module
M_TMS                in90JTAG Module
MIO10                inout29MIO
MIO11                inout19MIO
MIO12                inout36MIO
MIO13                inout30MIO
MIO14                inout37MIO / Module UART0.RX << BDBUS0
MIO15                in18MIO / Module UART0.TX >> BDBUS1
MODE                 out27Boot Mode for Zynq Devices (Flash or SD)
NOSEQ                inout21No Sequence, connected to Module CPLD / currently_not_used 
PG_C2M               out20Power Good for FMC
PGOOD                inout25connected to Module CPLD / currently_not_used
PHY_LED1             out42PHY LED
PHY_LED2             out43PHY LED
POK_FMC              in32FMC Power good from FMC VADJ DCDC
PX6                  inout49PMOD J2
PX7                  inout48PMOD J2 
RESIN                out13Module Reset
REVISION_DETECIONin57REV06+ only: Detection / currently_not_used
S1                   in3User Pushbutton
S2                   in2User Pushbutton / global Reset
SD_DETECT            in40SD Detection
SD_WP                in41SD
SEL_SD               out39SD Selection, MMC SD Slot or PMOD J2
ULED1                out78LED D1
ULED2                out77LED D2
ULED3                out76LED D3
ULED4                out16LED D4
ULED5                out69LED D5, powered by VIOTB (FMC VADJ)
ULED6                out68LED D6, powered by VIOTB (FMC VADJ)
ULED7                out65LED D7, powered by VIOTB (FMC VADJ)
ULED8                out64LED D8, powered by VIOTB (FMC VADJ)
USB_OC               in17USB Over Current
VID0                 out34VADJ Voltage selection (EN5335QI)
VID1                 out35VADJ Voltage selection (EN5335QI)
VID2                 out38VADJ Voltage selection (EN5335QI)
X6                   in60Module IO (powered by VIOTB (FMC VADJ))
Y0                   in75I2C SCL (powered by VIOTB (FMC VADJ))
Y1                   out66I2C SDA_OUT (powered by VIOTB (FMC VADJ))
Y2                   in67RGPIO CLK (powered by VIOTB (FMC VADJ))
Y3                   out70RGPIO TX (powered by VIOTB (FMC VADJ))
Y4                   in74RGPIO RX (powered by VIOTB (FMC VADJ))
Y5                   in71I2C SDA_IN (powered by VIOTB (FMC VADJ))
Y6                   in63Module IO (powered by VIOTB (FMC VADJ))

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Boot mode is set to SD-Boot, when SD-Card is detected.

FMC I2C

"3 wire split i2c" to to normal I2C:

Code Block
languageruby
FMC_SDA       <= '0' when Y5='0' else 'Z';
FMC_SCL       <= Y0 and PON;
Y1            <= FMC_SDA;



RGPIO

RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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modified-date
modified-date
dateFormatyyyy-MM-dd

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current-version
current-version
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REV05REV03,REV04,REV05,REV6

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modified-user
modified-user

Add FMC I2C description
2017-08-14v.27REV05REV03,REV04,REV05,REV6John HartfielDescription correction on port table
2017-06-08v.26REV05REV03,REV04,REV05,REV6John Hartfieldocument style update.
2016-11-29v.24REV05REV03,REV04,REV05,REV6John HartfielRevision 05 finished
2016-04-11

v.1

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created-user

Initial release
 All  

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modified-users

 

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