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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware



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Table of contents

Table of Contents
outlinetrue

Overview

CPLD Device with designator U14: LCMX02-1200HC

Feature Summary

  • Power Management
    • VADJ Configuration via DIP-Switch or I2C
  • Reset Management
  • Boot Mode Controller
  • FPGA UART routing
  • RGPIO Interface to FPGA

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
ACBUS4                96
 
FTDI / currently_not_used
ACBUS5                88
 
FTDI / currently_not_used
ADBUS4               
 
out98
 
constant 0 / currently_not_used
ADBUS7               
 
in97
 
/ currently_not_used
BDBUS0               
 
in87
 
UART TX from FTDI
BDBUS1               
 
out86
 
UART RX to FTDI
C_TCKout81
 
JTAG FTDI
C_TDIout84
 
JTAG FTDI
C_TDOin83
 
JTAG FTDI
C_TMSout85
 
JTAG FTDI
CM0                  in99
 
DIP Switch S3-M1
CM1                  in1
DIP Switch S3-M2

CM2

in51REV06+ only: DIP Switch S4-4 / RGPIO Bus (powered by VIOTB (FMC VADJ))
 
EN_FMC               
 
out31
 
VADJ and 3V3V_FMC Power on
EN1                  out24
 
Power Enable Pin for Module CPLD
FMC_PRSNT            
 
in28
 
FMC Card present pin (zero if not present)
FMC_SCL              
 
out10
 
FMC I2C
FMC_SDA
 
inout8
 
FMC I2C
FMC_TCK              
 
out4
 
JTAG FMC / currently_not_used
FMC_TDI              
 
out12
 
JTAG FMC / currently_not_used
FMC_TDO              
 
in9
 
JTAG FMC / currently_not_used
FMC_TMS              
 
out7
 
JTAG FMC / currently_not_used
HDMI_SCL             
 
inout47
 
HDMI / used also for I2C FMC control
HDMI_SDA             
 
inout45
 
HDMI / used also for I2C FMC control
HDMI_SPDIF           
 
out15
 
HDMI / currently_not_used
HDMI_SPDIFOUT        
 
in14
 
HDMI / currently_not_used
JTAGEN               
 
--82
 

Enable JTAG access to carrier CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)

Set DIP Switch S3-JTAGEN to ON, for module access.

M_TCK                in91
 
JTAG Module
M_TDI                in94
 
JTAG Module
M_TDO                out95
 
JTAG Module
M_TMS                in90
 
JTAG Module
MIO10                
 
inout29
 
MIO
MIO11                
 
inout19
 
MIO
MIO12                
 
inout36
 
MIO
MIO13                
 
inout30
 
MIO
MIO14                
 
inout37
 
MIO / Module UART0.RX << BDBUS0
MIO15                
 
in18
 
MIO / Module UART0.TX >> BDBUS1
MODE                 
 
out27
 
Boot Mode for Zynq Devices (Flash or SD)
NOSEQ                inout21No Sequence, connected to Module CPLD / currently_not_used 
PG_C2M               
 
out20
 
Power Good for FMC
PGOOD                
 
inout25
 
connected to Module CPLD / currently_not_used
PHY_LED1             
 
out42
 
PHY LED
PHY_LED2             
 
out43
 
PHY LED
POK_FMC              
 
in32
 
FMC Power good from FMC VADJ DCDC
PX6                  
 
inout49
 
PMOD J2
PX7                  
 
inout48
 
PMOD J2 
RESIN                out13
Module Reset
REVISION_DETECIONin57REV06+ only: Detection / currently_not_used
 
S1                   
 
in3
 
User Pushbutton
S2                   
 
in2
 
User Pushbutton / global Reset
SD_DETECT            
 
in40
 
SD Detection
SD_WP                
 
in41
 
SD
SEL_SD               
 
out39
 
SD Selection, MMC SD Slot or PMOD J2
ULED1                
 
out78
 
LED D1
ULED2                
 
out77
 
LED D2
ULED3                
 
out76
 
LED D3
ULED4                
 
out16
 
LED D4
ULED5                
 
out69
 
LED D5, powered by VIOTB (FMC VADJ)
ULED6                
 
out68
 
LED D6, powered by VIOTB (FMC VADJ)
ULED7                
 
out65
 
LED D7, powered by VIOTB (FMC VADJ)
ULED8                
 
out64
 
LED D8, powered by VIOTB (FMC VADJ)
USB_OC               
 
in17
 
USB Over Current
VID0                 
 
out34
 
VADJ Voltage selection (EN5335QI)
VID1                 
 
out35
 
VADJ Voltage selection (EN5335QI)
VID2                 
 
out38
 
VADJ Voltage selection (EN5335QI)
X6                   
 
in60
 
Module IO (powered by VIOTB (FMC VADJ))
Y0                   
 
in75
 
I2C SCL (powered by VIOTB (FMC VADJ))
Y1                   
 
out66
 
I2C SDA_OUT (powered by VIOTB (FMC VADJ))
Y2                   
 
in67
 
RGPIO CLK (powered by VIOTB (FMC VADJ))
Y3                   
 
out70
 
RGPIO TX (powered by VIOTB (FMC VADJ))
Y4                   
 
in74
 
RGPIO RX (powered by VIOTB (FMC VADJ))
Y5                   
 
in71
 
I2C SDA_IN (powered by VIOTB (FMC VADJ))
Y6                   
 
in63
 
Module IO (powered by VIOTB (FMC VADJ))

 

Functional Description

JTAG

JTAGEN set carrier board CPLD into the chain for firmware update. In normal mode JTAG is routed directly to Module. Set S3-ENJTAG to OFF to get access to carrier CPLD.

FMC JTAG is currently not enabled.

Power

EN1 is set to logical one .

EN_FMC is set to logical one or is controlled by I2C on I2C Mode.

PG_C2M is set to logical one or is controlled by I2C on I2C Mode.

VADJ

VADJ on PCB REV06+ S4 Control

This mode is only available on PCB Revision 06 or higher.

S4 control will be enabled on power on sequence or reset (S2-Button), if one of the three S4-DIP switches is set to one.

In this Mode I2C-controll is not selectable and S3-M1 and S3-M2 are available as User-DIP-Switch.

S4-3(VID2)S4-2(VID1)S4-1(VID0)Description
ONONONVADJ: 3.3V
ONONOFFVADJ: 2.5V
ONOFFONVADJ: 1.8V
ONOFFOFFVADJ: 1.5V
OFFONONVADJ: 1.25V
OFFONOFFVADJ: 1.2V
OFFOFFONVADJ: 0.8V (Do not use, not supported as IO standard)
OFFOFFOFFused to set VADJ control to REV05- or I2C control after power up sequence
VADJ on PCB REV05- S3 Control

S4 control will be disabled on power on sequence or reset (S2-Button), if all of the three S4-DIP switches is set to OFF or older PCB revision is used.

Note

Do not set S4-Switches to ON, if REV05- or I2C control is enabled.


S3-M1S3-M2Description
OFFOFFVADJ: 1.8V
OFFONVADJ: 2.5V
ONOFFVADJ: 3.3V
OnONI2C controlled
VADJ on I2C Control

Disable S4 Control (see VADJ on PCB REV05- S3 Control) and set S3-M1 and S3-M2 to on. I2C VADJ Control use TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA) connected to module FPGA PL side. I2C-GPIO controller device address is 0x22. Transmitted data will be converted to a 8-bit GPIO bus.

BitAccessDefaultDescription
7R/W0FMC - Enable
6R/W0VID2
5R/W0VID1
4R/W0VID0
3R/W0PG_C2M - Enable
2RxPOK_FMC (EN5335QI Power OK)
1Rxone: I2C Mode, zero: DIP Mode,
0RxVID Mode (zero: S4-DIP-controlled, one:  REV05-/I2C controlled)


VID2VID1VID0Description
000VADJ: 3.3V
001VADJ: 2.5V
010VADJ: 1.8V
011VADJ: 1.5V
100VADJ: 1.25V
101VADJ: 1.2V
110VADJ: 0.8V
111reserved

To read I2C with petalinux use i2cget -y 0 0x22.

  • -y: do not confirm input
  • 0: I2CBUS, use bus number, which is connected to TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA)
  • 0x22 I2C GPIO controller on TE0701 CPLD

To write I2C with petalinux use i2cset -y 0 0x22 0x80

  • -y: do not confirm input
  • 0: I2CBUS, use bus number, which is connected to TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA)
  • 0x22 I2C GPIO controller on TE0701 CPLD
  • 0x80: Enable FMC Power with VAD 3.3V, see I2C control table.

Reset

RESIN (negative Reset) to module, can be set by S2 button.

Boot Mode

Boot mode is set to SD-Boot, when SD-Card is detected.

FMC I2C

"3 wire split i2c" to to normal I2C:

Code Block
languageruby
FMC_SDA       <= '0' when Y5='0' else 'Z';
FMC_SCL       <= Y0 and PON;
Y1            <= FMC_SDA;



RGPIO

RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.

RGPIO Pin to FPGAValue
0MIO10
1MIO11
2MIO12
3MIO13
4MIO14
5MIO15
6PX6
7PX7
8S1
9CM0
10CM1
11CM2
12SD_WP
13SD_DETECT
14USB_OC
15POK_FMC
16FMC_PRSNT
17PGOOD
18NOSEQ
19unused
20X6
21Y6
22-23unused
24-27reserved
28-31Interface detection


RGPIO Pin from FPAGValue
0-7LED 1-8
8-9PHY_LED 1/2
10-23unused
24-27reserved
28-31Interface detection

LED

LEDDescription

ULED1

VADJ selection when RGPIO Bus is not active else RGPIO Bus Pin 0

VADJ selection: blink  when VCCIO(VIOTB/VADJ) is disabled else on when VADJ on PCB REV05- or I2C Control or off when VADJ on PCB REV06+ S4 Control 

ULED2I2C control mode  when RGPIO Bus is not active else RGPIO Bus Pin 1
ULED3UART to Module activity  when RGPIO Bus is not active else RGPIO Bus Pin 2
ULED4UART to FTDI activity  when RGPIO Bus is not active else RGPIO Bus Pin 3
ULED5BOOTMODE (on Flash, off SD)  when RGPIO Bus is not active else RGPIO Bus Pin 4
ULED6CM2 when RGPIO Bus is not active else RGPIO Bus Pin 5
ULED7X6 when RGPIO Bus is not active else RGPIO Bus Pin 6
ULED8Y6 when RGPIO Bus is not active else RGPIO Bus Pin 7


PHY LEDDescription
PHY_LED1Y2 when RGPIO Bus is not active else RGPIO Bus Pin 8
PHY_LED2Y4 when RGPIO Bus is not active else RGPIO Bus Pin 9

UART

ToFromDescription
MIO14BDBUS0Module UART0.RX
BDBUS1MIO15Module UART0.TX

 

Appx. A: Change History

...

Revision Changes

Older Revisions to REV05

  • Power Management
    • three VADJ Control Modi (REV06+ S4 Control, REV05- S3 Control and I2C Control)
  • Reset Management
    • only little changes
  • RGPIO Interface to FPGA
    • RGPIO support
  • LED
    • new Order and accessible by RGPIO

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
current-version
current-version
prefixv.


 

REV05REV03,REV04,REV05,REV6

Page info
modified-usersmodified-users

Work in progress

user
modified-user

Add FMC I2C description
2017-08-14v.27REV05REV03,REV04,REV05,REV6John HartfielDescription correction on port table
2017-06-08v.26REV05REV03,REV04,REV05,REV6John Hartfieldocument style update.
2016-11-29v.24REV05REV03,REV04,REV05,REV6John HartfielRevision 05 finished
2016-04-11

v.1

--- 

Page info
created-user
created-user

Initial release
 All  

Page info
modified-users
modified-users

 

Appx. B: Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices

...