Page History
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CPLD Device: LCMX02-1200HC
Firmware is available on TE0701 Download Area.
Feature Summary
- Power Management
- VADJ Configuration via DIP-Switch or I2C
- Reset Management
- Boot Mode Controller
- FPGA UART routing
- RGPIO Interface to FPGA
Firmware Revision and supported PCB Revision
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| S4-3(VID2) | S4-2(VID1) | S4-1(VID0) | Description |
|---|---|---|---|
| ON | ON | ON | VADJ: 3.3V |
| ON | ON | OFF | VADJ: 2.5V |
| ON | OFF | ON | VADJ: 1.8V |
| ON | OFF | OFF | VADJ: 1.5V |
| OFF | ON | ON | VADJ: 1.25V |
| OFF | ON | OFF | VADJ: 1.2V |
| OFF | OFF | ON | VADJ: 0.8V |
| OFF | OFF | OFF | used to set VADJ control to REV05- or I2C control after power up sequence |
VADJ on PCB REV05-
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S3 Control
S4 control will be disabled on power on sequence or reset (S2-Button), if all of the three S4-DIP switches is set to OFF or older PCB revision is used.
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| S3-M1 | S3-M2 | Description |
|---|---|---|
| OFF | OFF | VADJ: 1.8V |
| OFF | ON | VADJ: 2.5V |
| ON | OFF | VADJ: 3.3V |
| On | ON | I2C controlled |
VADJ on I2C Control
Disable S4 Control and set S3-M1 and S3-M2 to on. I2C VADJ Control use TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA) connected to module FPGA PL side. I2C-GPIO controller device address is 0x22. Transmitted data will be converted to a 8-bit GPIO bus.
| Bit | Access | Default | Description |
|---|---|---|---|
| 7 | R/W | 0 | FMC - Enable |
| 6 | R/W | 0 | VID2 |
| 5 | R/W | 0 | VID1 |
| 4 | R/W | 0 | VID0 |
| 3 | R/W | 0 | PG_C2M - Enable |
| 2 | R | x | POK_FMC (EN5335QI Power OK) |
| 1 | R | x | one: I2C Mode, zero: DIP Mode, |
| 0 | R | x | VID Mode (zero: S4-DIP-controlled, one: REV05-/I2C controlled) |
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RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.
| RGPIO Pin to FPGA | Value |
|---|---|
| 0 | MIO10 |
| 1 | MIO11 |
| 2 | MIO12 |
| 3 | MIO13 |
| 4 | MIO14 |
| 5 | MIO15 |
| 6 | PX6 |
| 7 | PX7 |
| 8 | S1 |
| 9 | CM0 |
| 10 | CM1 |
| 11 | CM2 |
| 12 | SD_WP |
| 13 | SD_DETECT |
| 14 | USB_OC |
| 15 | POK_FMC |
| 16 | FMC_PRSNT |
| 17 | PGOOD |
| 18 | NOSEQ |
| 19 | unused |
| 20 | X6 |
| 21 | Y6 |
| 22-23 | unused |
| 24-27 | reserved |
| 28-31 | Interface detection |
| RGPIO Pin from FPAG | Value |
|---|---|
| 0-7 | LED 1-8 |
| 8-9 | PHY_LED 1/2 |
| 10-23 | unused |
| 24-27 | reserved |
| 28-31 | Interface detection |
LED
| LED | Description |
|---|---|
ULED1 | blink when VCCIO(VIOTB/VADJ) is disabled else on when VADJ on PCB REV05- or I2C Control or off when VADJ on PCB REV06+ S4 Control |
| ULED2 | I2C control mode when RGPIO Bus is not active else RGPIO Bus Pin 1 |
| ULED3 | UART to Module activity when RGPIO Bus is not active else RGPIO Bus Pin 2 |
| ULED4 | UART to FTDI activity when RGPIO Bus is not active else RGPIO Bus Pin 3 |
| ULED5 | BOOTMODE (on Flash, off SD) when RGPIO Bus is not active else RGPIO Bus Pin 4 |
| ULED6 | CM2 when RGPIO Bus is not active else RGPIO Bus Pin 5 |
| ULED7 | X6 when RGPIO Bus is not active else RGPIO Bus Pin 6 |
| ULED8 | Y6 when RGPIO Bus is not active else RGPIO Bus Pin 7 |
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Appx. A: Change History and Legal Notices
Revision Changes
- Power Management
- three VADJ Control Modi (REV06+ S4 Control, REV05- S3 Control and I2C Control)
- Reset Management
- only little changes
- RGPIO Interface to FPGA
- RGPIO support
- LED
- new Order and accessible by RGPIO
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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