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Overview

Refer to https://wiki.trenz-electronic.de/display/PD/TE0841+TRM for online version of this manual and additional technical documentation of the product.

The Trenz Electronic TE0841-01 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale FPGA, 1 GByte of DDR4 SDRAM, 32 MByte QSPI Flash for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic 4 x 5 cm SoMs are mechanically compatible.

Key Features

• Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
• 2 banks of 512 MByte, 16 bit wide DDR4 SDRAM
• 256 Mbit (32 MByte) QSPI Flash
• 3 x Samtec Razor Beam LSHM B2B, 260 terminals total
  - User I/O: 60 x HR, 84 x HP
  - Serial transceiver: 8 x GTH lanes (TX/RX)
  - GT clock inputs: 2
• Clocking
  - Si5338 - 4 output PLLs, GT and PL clocks
  - 200 MHz LVDS oscillator
• All power supplies on-board, single power source operation
• Evenly spread supply pins for optimized signal integrity
• Size: 40 x 50 mm
• 3 mm mounting holes for skyline heat spreader
• Rugged for industrial applications

Additional assembly options for cost or performance optimization plus high volume prices are available on request.

Block Diagram

Image Removed

Figure 1: TE0841-01 block diagram.

Main Components

Image Removed Image Removed

Figure 2: TE0841-01 main components.

1. Xilinx Kintex UltraScale FPGA, U1
2. Ultra performance oscillator @25.000000 MHz, U3
3. 12A PowerSoC DC-DC converter (0.95V), U14
4. 12A PowerSoC DC-DC converter (0.95V), U7
5. Low-jitter precision LVDS oscillator @200.0000 MHz, U11
6. Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
7. Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
8. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
9. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
10. Samtec Razor Beam™ LSHM-130 B2B connector, JM3
11. Programmable quad clock generator, U2
12. 32 MByte QSPI Flash, U6
13. 4 Gbit DDR4 SDRAM, U4
14. 4 Gbit DDR4 SDRAM, U5
15. System Controller CPLD, U18
16. Low-dropout (LDO) linear regulator (MGTAUX), U9
17. Ultra-low power low-dropout (LDO) regulator (VBATT), U19

Initial Delivery State

...

Storage device name

...

Content

...

Notes

...

OTP Flash area

...

Empty

...

Table 1: TE0841-01 module initial delivery state of programmable on-board devices.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Table below lists bank number, bank type, B2B connection, I/O signal/LVDS pair count and power source for each FPGA PL I/O bank connected to the B2B connectors: 

...

Table 2: General overview of FPGA's PL I/O signals connected to the B2B connectors.

For detailed information about the pin out, please refer to the Pin-out Tables. 

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

...

• MGT_RX0_P
• MGT_RX0_N
• MGT_TX0_P
• MGT_TX0_N

...

• JM3-8
• JM3-10
• JM3-7
• JM3-9

...

• MGTHRXP0_225, Y2
• MGTHRXN0_225, Y1
• MGTHTXP0_225, AA4
• MGTHTXN0_225, AA3

...

• MGT_RX1_P
• MGT_RX1_N
• MGT_TX1_P
• MGT_TX1_N

...

• JM3-14
• JM3-16
• JM3-13
• JM3-15

...

• MGTHRXP1_225, V2
• MGTHRXN1_225, V1
• MGTHTXP1_225, W4
• MGTHTXN1_225, W3

...

• MGT_RX2_P
• MGT_RX2_N
• MGT_TX2_P
• MGT_TX2_N

...

• JM3-20
• JM3-22
• JM3-19
• JM3-21

...

• MGTHRXP2_225, T2
• MGTHRXN2_225, T1
• MGTHTXP2_225, U4
• MGTHTXN2_225, U3

...

• MGT_RX3_P
• MGT_RX3_N
• MGT_TX3_P
• MGT_TX3_N

...

• JM3-26
• JM3-28
• JM3-25
• JM3-27

...

• MGTHRXP3_225, P2
• MGTHRXN3_225, P1
• MGTHTXP3_225, R4
• MGTHTXN3_225, R3

...

• MGT_RX4_P
• MGT_RX4_N
• MGT_TX4_P
• MGT_TX4_N

...

• JM1-12
• JM1-10
• JM1-6
• JM1-4

...

• MGTHRXP0_224, AH2
• MGTHRXN0_224, AH1
• MGTHTXP0_224, AG4
• MGTHTXN0_224, AG3

...

• MGT_RX5_P
• MGT_RX5_N
• MGT_TX5_P
• MGT_TX5_N

...

• JM1-24
• JM1-22
• JM1-18
• JM1-16

...

• MGTHRXP1_224, AF2
• MGTHRXN1_224, AF1
• MGTHTXP1_224, AF6
• MGTHTXN1_224, AF5

...

• MGT_RX6_P
• MGT_RX6_N
• MGT_TX6_P
• MGT_TX6_N

...

• JM1-27
• JM1-25
• JM1-19
• JM1-17

...

• MGTHRXP2_224, AD2
• MGTHRXN2_224, AD1
• MGTHTXP2_224, AE4
• MGTHTXN2_224, AE3

...

• MGT_RX7_P
• MGT_RX7_N
• MGT_TX7_P
• MGT_TX7_N

...

• JM3-2
• JM3-4
• JM3-1
• JM3-3

...

• MGTHRXP3_224, AB2
• MGTHRXN3_224, AB1
• MGTHTXP3_224, AC4
• MGTHTXN3_224, AC3

Table 3: MGT lanes

Below are listed MGT banks reference clock sources.

...

Table 4: MGT reference clock sources.

JTAG Interface

JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.

...

JTAG Signal

...

B2B Connector Pin

...

System Controller CPLD I/O Pins

Special purpose pins are connected to the System Controller CPLD and have following default configuration:

...

Quad SPI Interface

Quad SPI Flash (U6) is connected to the FPGA configuration bank 0.

...

I2C Interface

There are two PL bank 65 IO pins (PLL_SCL and PLL_SDA) reserved as I²C bus connected to the Si5338 PLL quad clock generator. Default Si5338 PLL chip I²C bus slave address is 0x70.

Additionally, two PL bank 65 IO pins (B65_SCL and B65_SDA) connected to the B2B connector JM1 can be used for external I²C connectivity, otherwise these pins are ordinary IOs.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U18) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

Quad SPI Flash Memory

On-board QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q256A with 256-Mbit (32-MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Clocking

...

25.000000 MHz

...

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Overview

The Trenz Electronic TE0841-02 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale FPGA, 2 GByte of DDR4 SDRAM, 64 MByte QSPI Flash for configuration and operation and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic 4 x 5 cm SoMs are mechanically compatible.

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Refer to http://trenz.org/te0841-info for the current online version of this manual and other available documentation.

Key Features

• Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
• 2 banks of 1024 MByte DDR4 SDRAM, 32bit wide memory interface(each DDR 16bit separate)
• 512 Mbit (64 MByte) QSPI Flash
• 3 x Samtec Razor Beam LSHM B2B, 260 terminals total
  - 60 x HR I/Os
  - 84 x HP I/Os
  - 8 x GTH transceiver lanes (TX/RX)
  - 2 x MGT external clock inputs
• Clocking
  - Si5338 - 4 output PLLs, GT and PL clocks
  - 200 MHz LVDS oscillator
• All power supplies on-board, single power source operation
• Evenly spread supply pins for optimized signal integrity
• Size: 40 x 50 mm
• 3 mm mounting holes for skyline heat spreader
• Rugged for industrial applications

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Main Components

1. Xilinx Kintex UltraScale FPGA, U1
2. Ultra performance oscillator @25.000000 MHz, U3
3. 12A PowerSoC DC-DC converter (0.95V), U14
4. 12A PowerSoC DC-DC converter (0.95V), U7

5. Low-jitter precision LVDS oscillator @200.0000 MHz, U11

6. Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
7. Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
8. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
9. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
10. Samtec Razor Beam™ LSHM-130 B2B connector, JM3
11. Programmable quad clock generator, U2
12. 64 MByte QSPI Flash, U6
13. 8 Gbit DDR4 SDRAM, U4
14. 8 Gbit DDR4 SDRAM, U5
15. System Controller CPLD, U18Programmable Clock Generator
16. Low-dropout (LDO) linear regulator (MGTAUX), U9
17. Ultra-low power low-dropout (LDO) regulator (VBATT), U19

Initial Delivery State

Table 1: TE0841-02 module initial delivery state of programmable on-board devices

Boot Process

By default the configuration mode pins M[2:0] of the FPGA are set to QSPI mode (Master SPI), hence the FPGA is configured from serial NOR flash at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI flash memory.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector:

Table 2: General overview of FPGA's PL I/O signals connected to the B2B connectors

For detailed information about the pin out, please refer to the Pin-out Tables.

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MGT Lanes

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MGT lanes should be listed separately, as they are more specific than just general I/Os.  
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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 3: FPGA to B2B connectors routed MGT lanes overview

Below are listed MGT banks reference clock sources:

Table 4: MGT reference clock sources

JTAG Interface

JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.

Table 5: JTAG interface signals

System Controller CPLD I/O Pins

Special purpose pins are connected to the System Controller CPLD and have following default configuration:

Table 6: System Controller CPLD I/O pins

For detailed function of the pins and signals, the internal signal assignment and the implemented logic, look to the Wiki reference page of the module's SC CPLD or into its bitstream file.

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Quad SPI Interface

Quad SPI interface is connected to the FPGA configuration bank 0.

Table 7: Quad SPI interface signals and connections

I2C Interface

On-module I²C interface is routed  from PL bank 65 I/O pins (PLL_SCL and PLL_SDA) to the I²C interface of Si5338 PLL quad clock generator U2, also two further pins of bank 65 can be used as external I²C interface of the modue:

Table 8: I²C slave device addresses

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

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DDR Memory

By default TE0841 module has two K4A8G165WB-BIRC DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 2 GBytes of on-module RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-module QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q512A11G1240E with 512-Mbit (64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Programmable Clock Generator

There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

 Table 9: Programmable quad PLL clock generator inputs and outputs, *PCB REV01 is not programmed

Oscillators

The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Table 10: Reference clock signals

On-board LEDs

Table 11: On-board LEDs

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 12: Typical power consumption

 * TBD - To Be Determined soon with reference design setup.

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power Distribution Dependencies

See also Xilinx datasheet DS892 for additional information. User should also check related base board documentation when intending base board design for TE0841 module.

Power-On Sequence

The TE0841 SoM meets the recommended criteria to power up the Xilinx FPGA properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the FPGA chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Power Rails

Table 13: Module power rails

Bank Voltages

Table 14: Module PL I/O bank voltages

Board to Board Connector

Variants Currently In Production

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See also the current available variants on the Trenz Electronic shop page

Technical Specifications

Absolute Maximum Ratings

Table 16: Module absolute maximum ratings

Recommended Operating Conditions

Table 17: Module recommended operating conditions

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8 mm.

• PCB thickness: 1.65 mm.

• Highest part on PCB: approximately 3 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Revision History

Hardware Revision History

Table 18: Module hardware revision history

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Oscillators

The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

...

On-board LEDs

...

Power and Power-On Sequence

Power Supply

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

Power Consumption

...

 * TBD - To be determined.

Power-On Sequence

For highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

See also Xilinx datasheet DS892 for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0720 module.

Power Rails

...

Voltages on B2B

Connectors

...

B2B JM1 Pins

...

B2B JM2 Pins

...

Input/Output

...

VBAT_IN

...

Board to Board Connectors

...

Variants Currently In Production

...

FPGA Chip

...

...

...

Technical Specifications

Absolute Maximum Ratings

...

Parameter

...

Units

...

Reference Document

...

VIN supply voltage

...

V

...

...

...

...

...

...

...

...

...

...

...

...

Storage temperature

...

-40

...

+85

...

°C

...

Recommended Operating Conditions

...

...

...

...

...

...

...

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8 mm.

• PCB thickness: 1.6 mm.

• Highest part on PCB: approximately 3 mm. Please download the step model for exact numbers.

 All dimensions are given in millimeters.

 Image Removed   Image Removed

Weight

47 g - Plain module.

9 g - Set of bolts and nuts.

Revision History

Hardware Revision History

...

Notes

...

01

...

First production revision

...

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Image Removed

Document Change History

...

Date

...

Revision

...

Contributors

...

Description

...

...

Table 18: Document change history

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