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  • Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
  • 2 banks of 1024 MByte DDR4 SDRAM, 32bit wide memory interface(each DDR 16bit separate)
  • 512 Mbit (64 MByte) QSPI Flash
  • 3 x Samtec Razor Beam LSHM B2B, 260 terminals total
    - 60 x HR I/Os
    - 84 x HP I/Os
    - 8 x GTH transceiver lanes (TX/RX)
    - 2 x MGT external clock inputs
  • Clocking
    - Si5338 - 4 output PLLs, GT and PL clocks
    - 200 MHz LVDS oscillator
  • All power supplies on-board, single power source operation
  • Evenly spread supply pins for optimized signal integrity
  • Size: 40 x 50 mm
  • 3 mm mounting holes for skyline heat spreader
  • Rugged for industrial applications

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titleFigure 1: TE0841-02 block diagram


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Main Components

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titleFigure 2: TE0841-02 main components


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  1. Xilinx Kintex UltraScale FPGA, U1
  2. Ultra performance oscillator @25.000000 MHz, U3
  3. 12A PowerSoC DC-DC converter (0.95V), U14
  4. 12A PowerSoC DC-DC converter (0.95V), U7

  5. Low-jitter precision LVDS oscillator @200.0000 MHz, U11

  6. Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
  7. Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
  8. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
  9. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
  10. Samtec Razor Beam™ LSHM-130 B2B connector, JM3
  11. Programmable quad clock generator, U2
  12. 64 MByte QSPI Flash, U6
  13. 8 Gbit DDR4 SDRAM, U4
  14. 8 Gbit DDR4 SDRAM, U5
  15. System Controller CPLD, U18Programmable Clock Generator
  16. Low-dropout (LDO) linear regulator (MGTAUX), U9
  17. Ultra-low power low-dropout (LDO) regulator (VBATT), U19

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Storage device name

Content

Notes

System Controller CPLD

Default firmware-
OTP Flash areaEmptyNot programmed
Quad clock generator OTP areaEmptyprogrammedon PCB REV02 and newerNot programmed

Table 1: TE0841-02 module initial delivery state of programmable on-board devices

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titleFigure 3: TE0841-02 Power Distribution Diagram


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See also Xilinx datasheet DS892 for additional information. User should also check related base board documentation when intending base board design for TE0841 module.

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titleFigure 4: TE0841-02 Power-On Sequence Diagram


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Power Rails

Power Rail Name

B2B JM1 Pins

B2B JM2 Pins

Input/Output

Notes
VIN1, 3, 52, 4, 6, 8InputSupply voltage.
3.3VIN13, 15-InputSupply voltage.
B64_VCO9, 11-InputHR (High Range) bank voltage.
B66_VCO-1, 3InputHP (High Performance) bank voltage.
B67_VCO-7, 9InputHP (High Performance) bank voltage.
B68_VCO-5InputHP (High Performance) bank voltage.

VBAT_IN

79-InputRTC battery supply voltage.
3.3V-10, 12, 91OutputModule on-board 3.3V voltage level.

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Table 14: Module PL I/O bank voltages

Board to Board Connector

Include Page
4 x 5 SoM LSHM B2B Connectors
4 x 5 SoM LSHM B2B Connectors


Variants Currently In Production

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Variants Currently In Production

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Parameter

MinMax

Units

Reference Document

VIN supply voltage

-0.36.0

V

EN63A0QI, TPS74401RGW datasheets
3.3VIN supply voltage-0.13.4VXilinx datasheet DS892 (HR Bank VCCO)
VBAT_IN-0.36.0VTPS780xx datasheet
Supply voltage for HR I/O banks (VCCO)

-0.500

3.400

VXilinx datasheet DS892

Supply voltage for HP I/O banks (VCCO)

-0.500

2.000VXilinx datasheet DS892
I/O input voltage for HR I/O banks

-0.400

VCCO + 0.550

VXilinx datasheet DS892

I/O input voltage for HP I/O banks

-0.550

VCCO + 0.550

VXilinx datasheet DS892
I/O input voltage for SC CPLD U18-0.53.75VLCMXO2-256HC datasheet
GTH and GTY transceiver reference clocks absolute input voltage (MGT_CLK0, MGT_CLK2)-0.5001.320VXilinx datasheet DS892

GTH and GTY transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage

-0.500

1.260

VXilinx datasheet DS892

Storage temperature

-40

+100

°C

SML-P11 LED datasheet

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ParameterMinMaxUnitsReference Document
VIN supply voltage3.35.5VTPS82085SIL, TPS74401RGW datasheet
3.3VIN supply voltage3.33.4VXilinx datasheet DS892 (HR Bank VCCO)
VBAT_IN2.25.5VTPS780xx datasheet
Supply voltage for HR I/O banks (VCCO)1.140

3.400

VXilinx datasheet DS892

Supply voltage for HP I/O banks (VCCO)

0.950

1.890

VXilinx datasheet DS892

I/O input voltage for HR I/O banks

–0.200

VCCO + 0.20VXilinx datasheet DS892
I/O input voltage for HP I/O banks–0.200VCCO + 0.20VXilinx datasheet DS892
I/O input voltage for SC CPLD U18-0.33.6VLCMXO2-256HC datasheet

Industrial Module Operating Temperature Range

-4085°CXilinx datasheet DS892
Commercial Module Operating Temperature Range085°CXilinx DS892, Silicon Labs Si5338 datasheet

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Date
Revision
Contributors
Description
 Page info
modified-date
modified-date
dateFormatyyyy-MM-dd
 Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat
 Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat
  • correction delivery section
  • update key features, document history
2018-08-07v.69Ali Naseri
  • updated pictures main components
2018-07-13v.68Ali Naseri
  • PCB REV02
2018-07-10
 Jul 2018
v.58
John Hartfiel 
  • update links
2018-03-13
 Mar 2018
v.57Jan Kumann, Ali Naseri
  • Initial document.
--all

 Page info
infoTypeModified users
dateFormatyyyy-MM-dd
typeFlat
  • --
Table 18: Document change history.
Disclaimer
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IN:Legal Notices
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