Page History
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- Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
- 2 banks of 1024 MByte DDR4 SDRAM, 32bit wide memory interface(each DDR 16bit separate)
- 512 Mbit (64 MByte) QSPI Flash
- 3 x Samtec Razor Beam LSHM B2B, 260 terminals total
- 60 x HR I/Os
- 84 x HP I/Os
- 8 x GTH transceiver lanes (TX/RX)
- 2 x MGT external clock inputs - Clocking
- Si5338 - 4 output PLLs, GT and PL clocks
- 200 MHz LVDS oscillator - All power supplies on-board, single power source operation
- Evenly spread supply pins for optimized signal integrity
- Size: 40 x 50 mm
- 3 mm mounting holes for skyline heat spreader
- Rugged for industrial applications
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Photo shows similar TE0841-01
- Xilinx Kintex UltraScale FPGA, U1
- Ultra performance oscillator @25.000000 MHz, U3
- 12A PowerSoC DC-DC converter (0.95V), U14
- 12A PowerSoC DC-DC converter (0.95V), U7
Low-jitter precision LVDS oscillator @200.0000 MHz, U11
- Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
- Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
- Samtec Razor Beam™ LSHM-150 B2B connector, JM1
- Samtec Razor Beam™ LSHM-150 B2B connector, JM2
- Samtec Razor Beam™ LSHM-130 B2B connector, JM3
- Programmable quad clock generator, U2
- 64 MByte QSPI Flash, U6
- 8 Gbit DDR4 SDRAM, U4
- 8 Gbit DDR4 SDRAM, U5
- System Controller CPLD, U18Programmable Clock Generator
- Low-dropout (LDO) linear regulator (MGTAUX), U9
- Ultra-low power low-dropout (LDO) regulator (VBATT), U19
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Storage device name | Content | Notes | |
|---|---|---|---|
System Controller CPLD | Default firmware | - | |
| OTP Flash area | Empty | Not programmed | |
| Quad clock generator OTP area | Empty | programmed | on PCB REV02 and newerNot programmed |
Table 1: TE0841-02 module initial delivery state of programmable on-board devices
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| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| VIN supply voltage | 3.3 | 5.5 | V | TPS82085SIL, TPS74401RGW datasheet |
| 3.3VIN supply voltage | 3.3 | 3.4 | V | Xilinx datasheet DS892 (HR Bank VCCO) |
| VBAT_IN | 2.2 | 5.5 | V | TPS780xx datasheet |
| Supply voltage for HR I/O banks (VCCO) | 1.140 | 3.400 | V | Xilinx datasheet DS892 |
Supply voltage for HP I/O banks (VCCO) | 0.950 | 1.890 | V | Xilinx datasheet DS892 |
I/O input voltage for HR I/O banks | –0.200 | VCCO + 0.20 | V | Xilinx datasheet DS892 |
| I/O input voltage for HP I/O banks | –0.200 | VCCO + 0.20 | V | Xilinx datasheet DS892 |
| I/O input voltage for SC CPLD U18 | -0.3 | 3.6 | V | LCMXO2-256HC datasheet |
Industrial Module Operating Temperature Range | -40 | 85 | °C | Xilinx datasheet DS892 |
| Commercial Module Operating Temperature Range | 0 | 85 | °C | Xilinx DS892, Silicon Labs Si5338 datasheet |
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| 2018-08-07 | v.69 | Ali Naseri |
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| 2018-07-13 | v.68 | Ali Naseri |
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2018-07-10 | v.58 | John Hartfiel |
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2018-03-13 | v.57 | Jan Kumann, Ali Naseri |
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| -- | all |
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Table 18: Document change history
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