changes.mady.by.user John Hartfiel
Saved on 03 02, 2020
Saved on 12 02, 2020
The maximum power consumption of a module manly depends on the design which is running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to generate power consumption of the developed design with Vivado.
Please also observe the TRM of the Trenz Electronic module and the power management of our corresponding carrier boards.
Module pinout files can be generated with our Master Excel Pinout Sheet. You can also use the schematic on our download area.
Trenz Electronic Modules which are offered in the shop are listed on our shop page grouped by FPGA-Family. Wiki overview of the different series is available on Products
See Xilinx Answer Record: AR# 43989
Power sequencing of the FPGA/SoC banks and IOs must be still fulfil restrictions from manufacturer data sheet.
In most case IOs should be enabled after core voltages are powered on. Some module output voltage can be used to enable carrier power regulator for variable bank powers and connected periphery.
See also datasheet power sequencing of the section of the give device: