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The pin-assignment of the SFP connector is in detail as fellows:
| SFP+ pin | SFP+ pin netname | B2B |
|---|---|---|
| Transmit Data + (pin 18) | MGT_TX3_P | JB2-26 |
| Transmit Data - (pin 19) | MGT_TX3_N | JB2-28 |
| Receive Data + (pin 13) | MGT_RX3_P | JB2-25 |
| Receive Data - (pin 12) | MGT_RX3_N | JB2-27 |
| Receive Fault (pin 2) | MIO10 | JB1-96 |
| Receive disable (pin 3) | not connected | - |
| MOD-DEF2 (pin 4) | MIO13 | JB1-98 |
| MOD-DEF1 (pin 5) | MIO12 | JB1-100 |
| MOD-DEF0 (pin 6) | MIO11 | JB1-94 |
| RS0 (pin 7) | not connected | - |
| LOS (pin 8) | MIO0 | JB1-88 |
| RS1 (pin 9) | not connected | - |
Table 1: SFP+ connector pin-assignment
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The MGT-lane pins are bridged as fellows, if 4 x 5 SoM TE0741 is mounted:
| MGT-lane | B2B TX diff-pair | B2B RX diff-pair | B2B-pins bridged |
|---|---|---|---|
| MGT-lane 0 | JB2-8 (MGT_TX0_N) JB2-10 (MGT_TX0_P) | JB2-7 (MGT_RX0_N) JB2-9 (MGT_RX0_P) | JB2-7 to JB2-8 bridged JB2-9 to JB2-10 bridged |
| MGT-lane 1 | JB2-14 (MGT_TX1_N) JB2-16 (MGT_TX1_P) | JB2-13 (MGT_RX1_N) JB2-15 (MGT_RX1_P) | JB2-13 to JB2-14 bridged JB2-15 to JB2-16 bridged |
| MGT-lane 2 | JB1-20 (MGT_TX2_N) JB1-22 (MGT_TX2_P) | JB1-19 (MGT_RX2_N) JB1-21 (MGT_RX2_P) | JB1-19 to JB1-20 bridged JB1-21 to JB1-22 bridged |
| MGT-lane 7 | JB1-3 (MGT_TX7_P) JB1-5 (MGT_TX7_N) | JB1-9 (MGT_RX7_P) JB1-11 (MGT_RX7_N) | JB1-3 to JB1-9 bridged JB1-5 to JB1-11 bridged |
| MGT-lane 6 | JB1-15 (MGT_TX6_P) JB1-17 (MGT_TX6_N) | JB1-21 (MGT_RX6_P) JB1-23 (MGT_RX6_N) | JB1-15 to JB1-21 bridged JB1-17 to JB1-23 bridged |
Table 2: Bridging-table of the MGT-lanes for mounted 4 x 5 SoM TE0741.
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The JTAG-interface of the mounted 4 x 5 SoM can be accessed via header JX1. This header has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment.
| JX1 pin | JX1 pin net name | B2B |
|---|---|---|
| C (pin 4) | TCK | JB3-100 |
| D (pin 8) | TDO | JB3-98 |
| F (pin 10) | TDI | JB3-96 |
| H (pin 12) | TMS | JB3-94 |
| A (pin 3) | MIO15 | JB1-86 |
| B (pin 7) | MIO14 | JB1-91 |
| E (pin 9) | BOOTMODE (JTAGSELECT) | JB1-90 |
| G (pin 11) | RESIN | JB3-17 |
Table 3: JTAG header JX1 pin-assignment
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Power supply with minimum current capability of 3A at 12V 3.3V for system startup is recommended.
Power-On Sequence
The on-board voltages of the carrier board will be powered up simultaneously after one singlewith an external power-supply with a nominal voltage of 12V is connected to the power-jack J103.3V.
The PL IOexternal power-bank supply voltage FMC_VADJ will be available after the output of the 5.0V-DCDC-converter is active and the pin EN_FMC of the SC-CPLD is assertedcan be connected to the board by the following pins:
| Connector | 3.3V pin | GND pin |
|---|---|---|
| JX1 | JX1-5, JX1-6, | JX1-1, JX1-2 |
| J3 | J3-5, J3-6 | J3-1, J3-2 |
| J4 | J4-5 | J4-1, J4-2 |
| J20 | J20-5, J20-46 | J20-1 , J20-2 , J20-49 , J20-50 |
| J17 | J17-5, J17-46 | J17-1 , J17-2 , J17-49 , J17-50 |
Table 4: Connector-pins capable for external 3.3V power-supply
Power-On Sequence
The PL IO-bank supply-voltages 1.8V, 2.5V and 3.3V will be available after the mounted module's 3.3V voltage level is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
Note: The suppy-voltages have low current dropout.
Figure 3: Power-Up sequence diagram
Configuring VCCIO
On the TE0705 TEBA0841 carrier board different VCCIO configurations can be chosen by the jumper J21 and DIP-switch S3J26 and J27.
The purpose of the jumper and the DIP-switch S3 of the Carrier Board will be explained in the following sections.
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| Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
Vin supply voltage | 113.4135 | 123.6465 | V | 123.0V 3V supply-voltage ± 5% |
Storage Temperature | -55 | 125105 | °C Lattice MachX02 family data sheet | Molex 74441-0001 Product Specification |
Recommended Operating Conditions
| Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
| Vin supply voltage | 113.4135 | 123.6465 | V | - |
Physical Dimensions
Board size: PCB 170.4 mm × 98 mm. Notice that some parts the are hanging slightly over the edge of the PCB like the mini USB-jacks (ca. 1.4 mm) and the Ethernet RJ-45 jack (ca 2.2 mm), which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.
Mating height of the module with standard connectors: 8mm
PCB thickness: ca. 1.65mm
Highest part on the PCB is the Ethernet RJ-45 jack, which has an approximately 17 mm overall hight. Please download the step model for exact numbers.
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| Date | Revision | Notes | PCN | Documentation link |
|---|---|---|---|---|
| 2016-10-04 | 04 | |||
| - | 03 | |||
| - | 02 | |||
| - | 01 |
Figure 5: Hardware revision Number
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