Page History
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| Connector designator | pin-header layout | # IO's | # LVDS-pairs | available VCCIOsVCCIO's | interfaces |
|---|---|---|---|---|---|
| J4 | 2-row 10-pin | 6 | 0 | 3.3V M1.8VOUT from mounted module | SDIO (6 IO's allocated) voltage-translation via SDIO port expander (e.g. Texas Instruments TXS02612) necessary due to the different voltage levels of the Micro SD Card (3.3V) and MIO0-bank of the Xilinx Zynq-chip (1.8V) |
| J17 | 2-row 50-pin | 42 (Bank 13) | 21 | 3.3V VCCIOD | - |
| J20 | 2-row 50-pin | 42 (Bank 35) | 21 | 3.3V VCCIOA | - |
| J3 | 2-row 16-pin | 12 | 1 | 3.3V | JTAG (4 IO's allocated) UART (2 IO's allocated) Reference clock input MGT-CLK0 (1 LVDS-pair) |
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| Note |
|---|
Note: The corresponding PL IO-voltage supply voltages of the 4x5 SoM to the selectable base-board voltage VCCIOA and VCCIOD are depending on the mounted 4x5 SoM and varying in order of the used model. Refer to SoM's schematic to get information about the specific pin-assignment on module's B2B-connectors regarding PL IO-bank supply-voltages and to the 4x5 Module integration Guide for VCCIO voltage options. |
Following table describes how to configure the base-board supply-voltages by jumpers:
base-board supply-voltages vs voltage-levels | VCCIOA | VCCIOD |
|---|---|---|
| 1.8V | J26:1-2 | J27:1-2 |
| 2.5V | J26:3-4 | J27:3-4 |
| 3.3V | J26:5-6 | J27:5-6 |
Table 6: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2' means pins 1 and 2 are connected, 'Jx: 3-4' means pins 3 and 4 are connected, and so on.
| Note |
|---|
| It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4x5 module to avoid failures and damages to the functionality of the mounted SoM. |
Technical Specifications
Absolute Maximum Ratings
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