Page History
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| Connector designator | pin-header layout | # IO's | # LVDS-pairs | available VCCIO's | interfaces |
|---|---|---|---|---|---|
| J4 | 2-row 10-pin | 6 | 0 | 3.3V M1.8VOUT (from mounted module) | SDIO (6 IO's allocated) voltage-translation via SDIO port expander (e.g. Texas Instruments TXS02612) necessary due to the different voltage levels of the Micro SD Card (3.3V) and MIO0-bank of the Xilinx Zynq-chip (1.8V) |
| J17 | 2-row 50-pin | 42 (Bank 13) | 21 | 3.3V VCCIOD | - |
| J20 | 2-row 50-pin | 42 (Bank 35) | 21 | 3.3V VCCIOA | - |
| J3 | 2-row 16-pin | 12 | 1 | 3.3V | JTAG (4 IO's allocated) UART (2 IO's allocated) Reference clock input MGT-CLK0 (1 LVDS-pair) |
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