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The JTAG-interface of the mounted 4 x 5 SoM can be accessed via header JX1. This header has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment:
| JX1 pin | JX1 pin net-name | B2B |
|---|---|---|
| C (pin 4) | TCK | JB3-100 |
| D (pin 8) | TDO | JB3-98 |
| F (pin 10) | TDI | JB3-96 |
| H (pin 12) | TMS | JB3-94 |
| A (pin 3) | MIO15 | JB1-86 (usable as UART RX/TX-line) |
| B (pin 7) | MIO14 | JB1-91 (usable as UART RX/TX-line) |
| E (pin 9) | BOOTMODE | JB1-90 (JTAGSELECT) |
| G (pin 11) | RESIN | JB3-17 |
Table 3: JTAG header JX1 pin-assignment
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Following table gives a summary of the optional pin-headers of the base-board:
| Connector designator | pin-header layout | # IO's | # LVDS-pairs | available VCCIO's | interfaces |
|---|---|---|---|---|---|
| J4 | 2-row 10-pin | 6 | 0 | 3.3V M1.8VOUT (from mounted module) | SDIO (6 IO's allocated) voltage-translation via SDIO port expander (e.g. Texas Instruments TXS02612) necessary due to the different voltage levels of the Micro SD Card (3.3V) and MIO0-bank of the Xilinx Zynq-chip (1.8V) |
| J17 | 2-row 50-pin | 42 (Bank 13) | 21 | 3.3V VCCIOD | - |
| J20 | 2-row 50-pin | 42 (Bank 35) | 21 | 3.3V VCCIOA | - |
| J3 | 2-row 16-pin | 12 | 1 | 3.3V | JTAG (4 IO's allocated) UART (2 IO's allocated) Reference clock input MGT-CLK0 (1 LVDS-pair) |
Table 5: Summary of optional pin-headers
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The external power-supply can be connected to the board by the following pins:
| Connector | 3.3V pin | GND pin |
|---|---|---|
| JX1 | JX1-5, JX1-6, | JX1-1, JX1-2 |
| J3 | J3-5, J3-6 | J3-1, J3-2 |
| J4 | J4-5 | J4-1, J4-2 |
| J20 | J20-5, J20-46 | J20-1 , J20-2 , J20-49 , J20-50 |
| J17 | J17-5, J17-46 | J17-1 , J17-2 , J17-49 , J17-50 |
Table 4: Connector-pins capable for external 3.3V power-supply
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