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| Scroll Title |
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| anchor | Table_SIP_MGT |
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| title | MGT connections to B2B connector |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Lane | Bank | Type | Signal Name | B2B Pin | Note |
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| 0 | 112 | GTX | MGT_RX0_P MGT_RX0_N MGT_TX0_P MGT_TX0_N | J3-50 J3-52 J3-51 J3-53 |
| | 1 | 112 | GTX | MGT_RX1_P MGT_RX1_N MGT_TX1_P MGT_TX1_N | J3-56 J3-58 J3-57 J3-59 |
| | 2 | 112 | GTX | MGT_RX2_P MGT_RX2_N MGT_TX2_P MGT_TX2_N | J3-62 J3-64 J3-63 J3-65 |
| | 3 | 112 | GTX | MGT_RX3_P MGT_RX3_N MGT_TX3_P MGT_TX3_N | J3-68 J3-70 J3-69 J3-71 |
| | 4 | 111 1) | GTX | MGT_RX4_P MGT_RX4_N MGT_TX4_P MGT_TX4_N | J1-23 J1-21 J1-22 J1-20 |
| | 5 | 111 1) | GTX | MGT_RX5_P MGT_RX5_N MGT_TX5_P MGT_TX5_N | J1-17 J1-15 J1-16 J1-14 |
| | 6 | 111 1) | GTX | MGT_RX6_P MGT_RX6_N MGT_TX6_P MGT_TX6_N | J1-11 J1-9 J1-10 J1-8 |
| | 7 | 111 1) | GTX | MGT_RX7_P MGT_RX7_N MGT_TX7_P MGT_TX7_N | J1-5 J1-3 J1-4 J1-2 |
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1) Note: MGT bank 111 not available at XC7Z030 Zynq SoC.
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| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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| Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
|---|
| PL_VIN | 147, 149, 151, 153,
155, 157, 159 | - | - | Input | module supply voltage | | PS_VIN | - | 154, 156, 158 | - | Input | module supply voltage | | PS_3.3V | - | 160 | - | Input | module supply voltage | | VCCIO12 | 54, 55 | - | - | Input | high range bank I/O voltage | | VCCIO13 | 112, 113 | - | - | Input | high range bank I/O voltage | | VCCIO33 | - | - | 115, 120 | Input | high performance bank I/O voltage | | VCCIO34 | - | 29, 30 | - | - | Input | high performance bank I/O voltage | | VCCIO35 | - | 87, 88 | - | - | Input | high performance bank I/O voltage | | VBAT_IN | 146 | - | - | Input | RTC (battery-backed) supply voltage | | PS_1.8V | - | 130 | - | Output | internal 1.8V voltage level (Process System) | | PL_1.8V | - | - | 84,85 | Output | internal 1.8V voltage level (FPGA) |
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| Scroll Title |
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| anchor | Table_RH_DCH |
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| title | Document change history. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Contributor | Description |
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| Page info |
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| infoType | Modified date |
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| dateFormat | yyyy-MM-dd |
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| type | Flat |
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| | Page info |
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| infoType | Current version |
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| prefix | v. |
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| type | Flat |
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| showVersions | false |
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| | Page info |
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| infoType | Modified by |
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| type | Flat |
|---|
| showVersions | false |
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|
| | | 2019-11-19 | v.93 | John Hartfiel | | | 2019-10-10 | v.92 | Pedram Babakhani | document style update - description bug fix
| | 2019-03-01 | v.83 | | | | 2018-04-11 | v.81 | John Hartfiel | | | 2017-11-14 | v.80 | John Hartfiel | | | 2017-11-13 | v.79 | Ali Naseri, Jan Kumann, John Hartfiel | | -- | all | | Page info |
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| infoType | Modified users |
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| type | Flat |
|---|
| showVersions | false |
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