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CPLD Device: LCMX02-256HC

Feature Summary

JTAG routing

Pinheader routing

Firmware Revision and supported PCB Revision

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Product Specification

Port Description

 

Name / opt. VHD NameDirectionPinDescription
Ain8XMOD Pin Header /
ACBUS4 27FTDI / currently_not_used
ACBUS5 28FTDI / currently_not_used
ADBUS4 
5FTDI / currently_not_used
Bout12XMOD Pin Header /
BDBUS2in21FTDI / currently_not_used
BDBUS3out20FTDI / currently_not_used
Cout9XMOD Pin Header /
Din11XMOD Pin Header /
Ein14XMOD Pin Header /
Fout13XMOD Pin Header /
FT_B_RX / BDBUS1out25FTDI
FT_B_TX / BDBUS0in23FTDI
Gin17XMOD Pin Header / Pushbutton S1
Hout16XMOD Pin Header /
JTAGENin26Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over S2-1
TCK / ADBUS0in30FTDI
TDI / ADBUS1in32FTDI
TDO / ADBUS2out1FTDI
TMS / ADBUS3in29FTDI
ULEDout10LED D4 (RED)
XCLKin412 MHz OSCI Ref CLK / currently_not_used
 

 

Functional Description

JTAG

Power

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JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA).

UART

UART is routed through the CPLD.

 OutputInput
BBDBUS0
BDBUS1A

LED

ULED is E xor not G

Appx. A: Change History and Legal Notices

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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dateFormatyyyy-MM-dd

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 REV01 REV02

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Work in progress
2016-04-11

v.1

--- REV02

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Initial release
 All  
 

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