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Table of Contents

Table of Contents

Overview

Scroll Only (inline)
Refer to https://

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wiki.trenz-electronic.de/

...

display/

...

PD/TE0726+TRM for

...

online version of this manual and additional technical documentation of the product.


 The Trenz Electronic TE0726 "ZynqBerry" is a industrial-grade Raspberry Pi form-factor compatible FPGA SoM (System on Module) based on Xilinx Zynq-7010 SoC (XC7Z010 System on Chip) with up to 512 MByte DDR3L SDRAM, 4 x USB 2.0 ports, 10/100 Mbit Ethernet port and 16 MByte Flash memory. All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Block Diagram

Image Removed

Main Components

Image Removed

Image Removed

  1. Xilinx Zynq XC7Z010 All Programmable SoC, U1
  2. 512 MByte DDR3L SDRAM, U8
  3. Lattice Semiconductor MachXO2 System Controller CPLD, U11
  4. Dual high-speed USB to multipurpose UART/FIFO, U3
  5. 2 Kbit Microwire compatible serial EEPROM, U6
  6. Low-power, programmable oscillator @ 12.000000 MHz, U7
  7. Ultra-low capacitance double rail-to-rail ESD protection diode ,U4
  8. Micro-USB 2.0 B receptacle, J1
  9. Green LED (GLED), D1
  10. Red LED (RLED), D2
  11. DSI LCD connector, J4
  12. JTAGENB, when low, TDO, TDI, TMS and TCK function as GPIOs, J15
  13. Fiducial mark PM2
  14. External I2C bus with interrupt signal and power line, J2
  15. Low-voltage 4-channel I2C and SMBus multiplexer with interrupt logic, U10
  16. 2x20 pin 2.54 GPIO header, J8

  17. 128 Mbit (16 MByte) 3.0V SPI Flash memory, U5

  18. USB 2.0 Hub and 10/100 Ethernet controller, U2
  19. External reset
  20. 2 Kbit Microwire compatible serial EEPROM, U9
  21. PUDC of Zynq, active low enables  internal pull-ups during configuration on all SelectIO pins
  22. Dual USB A receptacle, J12. Also fiducial mark PM1
  23. Dual USB A receptacle, J11
  24. Low power programmable oscillator @ 25.000000 MHz, U13
  25. Molex’s miniature traceability S/N pad for low-cost, unique product identification
  26. RJ-45 Ethernet connector with 10/100 integrated magnetics, J10. Also fiducial mark PM3
  27. 3.5mm RCA audio jack, J7
  28. 1A PowerSoC synchronous buck regulator with integrated inductor (3.3V), U20
  29. 1A PowerSoC synchronous buck regulator with integrated inductor (1.8V), U19
  30. ZIF FFC/FPC CSI-2 camera connector, J3
  31. HDMI connector, J6

  32. Common mode filter with ESD protection, D8

  33. Common mode filter with ESD protection, D9

  34. 1A PowerSoC synchronous buck regulator with integrated inductor (1.35V), U16
  35. Additional external +5V power supply connector, J5

  36. Highly integrated full featured hi-speed USB 2.0 ULPI transceiver, U18

  37. Low-power programmable oscillator @ 33.333333 MHz, U14
  38. Ultra-low supply current voltage monitor with optional watchdog, U22
  39. Fiducial mark PM4
  40. Micro SD memory card connector with detect switch, J9
  41. JTAG interface, TP1 (TDI), TP3 (TDO), TP5 (TCK), TP7 (TMS)
  42. 1A PowerSoC synchronous buck regulator with integrated inductor (1.0V), U17
  43. Fiducial mark PM6
  44. 0.5A dual channel current-limited power switch, U15
  45. 0.5A dual channel current-limited power switch, U21
  46. Fiducial mark PM5

Key Features

  • Xilinx Zynq XC7Z010-1CLG225C
    - REV3: DDR3L SDRAM (512MByte)
    - REV2: DDR3L SDRAM (128 - 512 MByte)
    - REV1 LPDDR2 SDRAM (64 MByte)
  • 16 MByte Flash
  • Raspberry Pi Model 2 form factor
  • LAN9514 USB Hub with 10/100 Ethernet
    - 4 x USB 2.0 with power switches
    - 10/100 Mbit Ethernet RJ45
  • Micro SD card slot with card-detect switch
  • HDMI connector
  • DSI connector (Display)
  • CSI-2 connector (Camera)
  • HAT header with 26 I/Os
  • Micro-USB
    - power input
    - USB UART
    - JTAG ARM- and FPGA-Debug
  • 3.5 mm audio plug (PWM audio output only)

Key Features

  • Xilinx Zynq XC7Z010-1CLG225C
    - REV3: DDR3L SDRAM (512 MByte)
    - REV2: DDR3L SDRAM (128 - 512 MByte)
    - REV1: LPDDR2 SDRAM (64 MByte)
  • 16 MByte Flash
  • Raspberry Pi Model 2 form factor
  • LAN9514 USB hub with 10/100 Ethernet
    - 4 x USB 2.0 with power switches
    - 10/100 Mbit Ethernet RJ45
  • Micro SD card slot with card-detect switch
  • HDMI connector
  • DSI connector (Display)
  • CSI-2 connector (Camera)
  • HAT header with 26 I/Os
  • Micro-USB
    - power input
    - USB UART
    - JTAG ARM- and FPGA-Debug
  • 3.5 mm stereo audio socket (PWM audio output only)
    Page break

Block Diagram

Image Added

Main Components

Image Added

Image Added

  1. Xilinx Zynq XC7Z010 All Programmable SoC, U1
  2. 512 MByte DDR3L SDRAM, U8
  3. Lattice Semiconductor MachXO2 System Controller CPLD, U11
  4. Dual high-speed USB to multipurpose UART/FIFO, U3
  5. 2 Kbit Microwire compatible serial EEPROM, U6
  6. Low-power, programmable oscillator @ 12.000000 MHz, U7
  7. Ultra-low capacitance double rail-to-rail ESD protection diode ,U4
  8. Micro-USB 2.0 B receptacle, J1
  9. Green LED (GLED), D1
  10. Red LED (RLED), D2
  11. DSI LCD connector, J4
  12. JTAGENB, when low, TDO, TDI, TMS and TCK function as GPIOs, J15
  13. Fiducial mark PM2
  14. External I2C bus with interrupt signal and power line, J2
  15. Low-voltage 4-channel I2C and SMBus multiplexer with interrupt logic, U10
  16. 2x20 pin 2.54 GPIO header, J8

  17. 128 Mbit (16 MByte) 3.0V SPI Flash memory, U5

  18. USB 2.0 Hub and 10/100 Ethernet controller, U2
  19. External reset
  20. 2 Kbit Microwire compatible serial EEPROM, U9
  21. PUDC of Zynq, active low enables  internal pull-ups during configuration on all SelectIO pins
  22. Dual USB A receptacle, J12. Also fiducial mark PM1
  23. Dual USB A receptacle, J11
  24. Low power programmable oscillator @ 25.000000 MHz, U13
  25. Molex’s miniature traceability S/N pad for low-cost, unique product identification
  26. RJ-45 Ethernet connector with 10/100 integrated magnetics, J10. Also fiducial mark PM3
  27. 3.5mm RCA audio jack, J7
  28. 1A PowerSoC synchronous buck regulator with integrated inductor (3.3V), U20
  29. 1A PowerSoC synchronous buck regulator with integrated inductor (1.8V), U19
  30. ZIF FFC/FPC CSI-2 camera connector, J3
  31. HDMI connector, J6

  32. Common mode filter with ESD protection, D8

  33. Common mode filter with ESD protection, D9

  34. 1A PowerSoC synchronous buck regulator with integrated inductor (1.35V), U16
  35. Additional external +5V power supply connector, J5

  36. Highly integrated full featured hi-speed USB 2.0 ULPI transceiver, U18

  37. Low-power programmable oscillator @ 33.333333 MHz, U14
  38. Ultra-low supply current voltage monitor with optional watchdog, U22
  39. Fiducial mark PM4
  40. Micro SD memory card connector with detect switch, J9
  41. JTAG interface, TP1 (TDI), TP3 (TDO), TP5 (TCK), TP7 (TMS)
  42. 1A PowerSoC synchronous buck regulator with integrated inductor (1.0V), U17
  43. Fiducial mark PM6
  44. 0.5A dual channel current-limited power switch, U15
  45. 0.5A dual channel current-limited power switch, U21
  46. Fiducial mark PM5

Initial Delivery Initial Delivery State

Up on delivery from Trenz Electronic System Controller CPLD is programmed with the standard firmware and FTDI FT2232H EEPROM contains pre-programmed Digilent license needed by Xilinx software tools for JTAG access, all other programmable devices are empty.

...

FPGA BankZynq PinSignal NameConnected To
35F13DSI_D0_R_NDSI display connector J4
35F14DSI_D0_R_PDSI display connector J4
35F12DSI_D1_R_NDSI display connector J4
35E13DSI_D1_R_PDSI display connector J4
35E11DSI_C_R_NDSI display connector J4
35E12DSI_C_R_PDSI display connector J4

See also section FPGA IO Banks Pin Mapping, pins DSI_XA and DSI_XB.

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Micro SD memory card connector J9 with detect switch is connected to the Zynq Soc PS MIO bank 500. See also section Default MIO Mapping.

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FPGA IO Banks Pin Mapping

BankZynq PinNameConnected To
34G14PUDCJumper J14
35G15DSI_XASystem Controller CPLD, pin 16
35F15DSI_XBSystem Controller CPLD, pin 17
Page break

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Header J8 Interface Mapping

26 PL IO  and 2 MIO IOs over I2C mux. All Bank IO voltages are 3.3V.

GPIO
J8 Pin
NameZynq Pin
J8

Zynq Pin
 
GPIO
Name
Zynq PinK15
J8 Pin
GPIO2
13.3V
 
-
GPIO15

-
N13
5V
10
2
GPIO3
3
J14
GPIO2
5
K15
 

-
GPIO16
5V
L13
4
36
5
GPIO4
GPIO3
H12
J14
7

-
 
GND
GPIO17
6
G11
7
11
GPIO4
GPIO5
H12
N14

M12
29
GPIO14
 
8
GPIO18
9
H11
GND
12
-
GPIO6

N13
R15
GPIO15
31
10
 
11
GPIO19
GPIO17
R12
G11
35

H11
GPIO7
GPIO18
L14
12
26
13
 
GPIO27
GPIO20
G12
M14

-
38
GND
GPIO8
14
L15
15
24
GPIO22
 
H13
GPIO21

J11
P15
GPIO23
40
16
GPIO9
17
J13
3.3V
21
-
 

K11
GPIO22
GPIO24
H13
18
15
19
GPIO19
GPIO10H14
-GND
19
20
 
21
GPIO23
GPIO9
J11
J13
16

K13
GPIO11
GPIO25
J15
22
23
 
GPIO11
GPIO24
J15
K11

L15
18
GPIO8
GPIO12
24
M15
25
32
GND
 
-
GPIO25

L14
K13
GPIO7
22
26
GPIO13R13
27MIO49(ID_SDA via TCA9544APWR) 
33

 
GPIO26L1237GPIO14M128 GPIO27G1213

Default MIO Mapping

Bank 500 MIOs

...

MIO

...

MIO0_INT

...

MIO48 (ID_SCL via TCA9544APWR )28
29GPIO5N14
-GND30
31GPIO6R15
M15GPIO1232
33GPIO13R13
-GND34
35GPIO19R12
L13GPIO1636
37GPIO26L12
M14GPIO2038
39GND-
P15GPIO2140

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Default MIO Mapping

Bank 500 MIOs

MIO

FunctionNotes
0

MIO0_INT

Interrupt signal from I2C MUX.
1SPI0_CSSPI chip select.
2SPI0_DQ0/M0Bi-directional data line 0
3SPI0_DQ1/M1Bi-directional data line 1
4SPI0_DQ2/M2Bi-directional data line 2
5SPI0_DQ3/M3Bi-directional data line 3
6SPI0_SCKSPI clock.
7MIO7RESETB of USB3320 chip, U18
8MIO8System Controller CPLD pin 28
9MIO9System Controller CPLD pin 29
10SD_D0Serial data 0.
11SD_CMDCommand/Response.
12SD_CLKSerial clock.
13SD_D1Serial data 1.
14SD_D2Serial data 2.
15SD_D3Serial data 3.

Page break

Bank 501 MIOs

 MIOFunctionNotes
28OTG-DATA4

Bank 501 MIOs

 MIOFunctionNotes28OTG-DATA4ULPI bi-directional data bus.29OTG-DIRData bus direction control signal.30OTG-STPData throttle signal.31OTG-NXTData stream stop.32OTG-DATA0ULPI bi-directional data bus.33OTG-DATA1ULPI bi-directional data bus.34OTG-DATA2ULPI bi-directional data bus.35OTG-DATA3ULPI bi-directional data bus.36OTG-CLKULPI clock.37OTG-DATA5
ULPI bi-directional data bus.
38
29OTG-
DATA6
DIRData bus direction control signal.
30OTG-STPData throttle signal.
31OTG-NXTData stream stop.
32OTG-DATA0
ULPI bi-directional data bus.39OTG-DATA7
ULPI bi-directional data bus.
48MUX_SCLI2C clock to I2C MUX.49MUX_SDAI2C data to/from I2C MUX.52MIO52System Controller CPLD pin 2053MIO53System Controller CPLD pin 21

LED's

There are two LEDs on TE0726 module:

33OTG-DATA1ULPI bi-directional data bus.
34OTG-DATA2ULPI bi-directional data bus.
35OTG-DATA3ULPI bi-directional data bus.
36OTG-CLKULPI clock.
37OTG-DATA5ULPI bi-directional data bus.
38OTG-DATA6ULPI bi-directional data bus.
39OTG-DATA7ULPI bi-directional data bus.
48MUX_SCLI2C clock to I2C MUX.
49MUX_SDAI2C data to/from I2C MUX.
52MIO52System Controller CPLD pin 20
53MIO53System Controller CPLD pin 21

On-board LEDs

There are two LEDs on TE0726 module:

LED

Signal Name

Color

CPLD Pin

Notes

D1GLEDGreen5CPLD bank 3.

D2

RLED

Red

LED

Signal Name

Color

CPLD Pin

Notes

D1GLEDGreen5CPLD bank 3.

D2

RLED

Red

4

CPLD bank 3.

On-board Peripherals

...

There is a System Controller CPLD chip LCMXO2-256HC from Lattice Semiconductor on-board. Refer to the TE0726 CPLD for more information.

Clocking

...

Signal Name

...

Default Frequency

...

Destination IC

...

Pin

...

Notes

...

33.333333 MHz

...

U1

...

C7

...

12.000000 MHz

...

U3

...

3

...

FT2232H oscillator input.

...

Hi-speed USB 2.0 and 10/100 Mbit Ethernet

The TE0726-03 has on-board SMSC LAN9514 controller featuring USB 2.0 hub and 10/100 Mbit Ethernet controller. USB hub has four downstream ports and one upstream port, fully compliant with Universal Serial Bus Specification Revision 2.0. HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) compatible. Upstream port is connected to the SMSC USB3320 hi-speed USB 2.0 ULPI transceiver which has full support for the optional On-The-Go (OTG) protocol.

High-Performance 10/100 Ethernet controller integrated into the same LAN9514 IC is fully compliant with IEEE802.3/802.3u standards, has integrated Ethernet MAC and PHY and supports both 10BASE-T and 100BASE-TX media.

256-byte EEPROM is connected via Microwire to the LAN9514 chip to store MAC address.

USB to JTAG/UART

The TE0726-03 has on-board high-speed USB 2.0 to UART/FIFO FT2232H controller from FTDI with external connection to micro-USB connector J1. There is also a 256-byte EEPROM wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools.

 

Warning

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

4-Channel I2C Multiplexer

Zynq MIO pin 48 (MUX_SCL) and pin 49 (MUX_SDA) are connected to the 4-channel I2C multiplexer chip TCA9544A from Texas Instruments having I2C address of 0x70. It has four slave I2C channels which are routed as follows:

...

Quad SPI Flash Memory

On-board QSPI flash memory (U5) on the TE0726 is provided by Cypress Semiconductor Serial NOR Flash Memory S25FL127SABMFV10 with 128 Mbit (16 MByte) storage capacity connected to the PS MIO bank (MIO1 ... MIO6) of the Zynq SoC. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq PS MIO-bank allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

DDR3L SDRAM

The TE0726 SoM is equipped with one DDR3L-1600 SDRAM module with 1 GByte memory density. The SDRAM module is connected to the Zynq SoC's PS DDR controller with 16-bit data bus-width.

Clocking

Signal Name

Clock IC

Default Frequency

Destination IC

Pin

Notes

PS_CLKU14

33.333333 MHz

U1

C7

Zynq SoC system reference clock.
OSCIU7

12.000000 MHz

U3

3

FT2232H oscillator input.

CLK24MU224 MHz (see also REFSEL0 .. 2)U1826Reference input/output clock, see datasheet.
CLK25MU1325.000000 MHzU261External 25 MHz crystal input.

Hi-speed USB 2.0 and 10/100 Mbit Ethernet

The TE0726-03 has on-board SMSC LAN9514 controller featuring USB 2.0 hub and 10/100 Mbit Ethernet controller. USB hub has four downstream ports and one upstream port, fully compliant with Universal Serial Bus Specification Revision 2.0. HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) compatible. Upstream port is connected to the SMSC USB3320 hi-speed USB 2.0 ULPI transceiver which has full support for the optional On-The-Go (OTG) protocol.

High-Performance 10/100 Ethernet controller integrated into the same LAN9514 IC is fully compliant with IEEE802.3/802.3u standards, has integrated Ethernet MAC and PHY and supports both 10BASE-T and 100BASE-TX media.

256-byte EEPROM is connected via Microwire to the LAN9514 chip to store MAC address.

USB to JTAG/UART

The TE0726-03 has on-board high-speed USB 2.0 to UART/FIFO FT2232H controller from FTDI with external connection to micro-USB connector J1. There is also a 256-byte EEPROM wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools.

 

Warning

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

4-Channel I2C Multiplexer

Zynq MIO pin 48 (MUX_SCL) and pin 49 (MUX_SDA) are connected to the 4-channel I2C multiplexer chip TCA9544A from Texas Instruments having I2C address of 0x70. It has four slave I2C channels which are routed as follows:

Channel

Connected To

0

Connector J8, pin 27 (ID_SDA) and pin 28 (ID_SCL).

1

DSI connector J4, pin 12 (DSI_SDA) and pin 11 (DSI_SCL).

2

HDMI connector J6, pin 16 (SDA) and pin 15 (SCL).

3

CSI-2 camera connector J3, pin 14 (CSI_SDA) and pin 13 (CSI_SCL).

Each slave channel of TCA9544A has its own dedicated interrupt signal in order for the master to detect an interrupt on the INT output pin that can result from any of the slave devices connected to the INT0-INT3 input pins.

Boot Process

Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader.

At least FSBL must be loaded from on-board SPI Flash, later all boot process can continue from SD Card. The easiest solution is to let FSBL to load bitstream and u-boot from SPI Flash, and then let u-boot to load Linux or any other OS image from SD Card.

...

Power and Power-On Sequence

Power Consumption

TE0726 needs one single power source via Micro USB2.0 B socket J1. However, it is recommended to not use any USB equipment below USB standard 2.0 to power the module. Also two-pin header J5 can be used as alternative to feed the 5V power supply voltage.

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

To power-up a module, 5.0V power

Boot Modes

Xilinx Zynq devices in CLG225 package do not not support SD Card boot directly from ROM bootloader.

At least FSBL must be loaded from on-board SPI Flash, later all boot process can continue from SD Card. The easiest way is to let FSBL to load bitstream and u-boot from SPI Flash, and then let u-boot to load linux or any other OS image from SD Card.

Power and Power-On Sequence

...

supply with minimum current capability of 1A is recommended.

Power

...

TE0726 needs one single power source via micro-USB jack J1. However it is recommended to not use any USB equipment below USB standard 2.0 to power the module. Also two-pin header J5 can be used to provide power source if needed.

Power-On Sequence

Distribution Dependencies

There is no specific power-on sequence, except to achieve minimum current draw, I/Os should be 3-stated at power-on.

There are following dependencies how the power supply voltage (5V nominal) is distributed to the on-board DC-DC converters.


...

Image Added


Power Rails and Bank Voltages

Rail/Bank

Name

Voltage

Notes

VCCINTVCCINT1.0V

...

PL internal supply voltage.
VCCPINTVCCPINT1.0VPS internal logic supply voltage.
VCCPLLVCCPLL1.8V

...

PS PLL supply.
VCCBATT_0VCCBATT_01.8V 
VCCAUXVCCAUX1.8V

...

PL auxiliary supply voltage.
VCCPAUXVCCPAUX1.8V

...

PS auxiliary supply voltage.
VCCADC_0VCCADC_01.8V 
RSVDVCC1..3RSVDVCC1..33.3V 
0VCCO_0

...

34

...

3.3V

...

1.8V

...

 

...

502

...

1.35V

...

Variants Currently in Production

...

RAM

...

Technical Specifications

3.3VConfiguration bank.

34

VCCO_34

3.3V

PL HR I/O bank.
35VCCO_35

1.8V

PL HR I/O bank.

500VCC_MIO_5003.3VPS MIO bank.
501VCC_MIO_5013.3VPS MIO bank.

502

VCCO_DDR_502

1.35V

DDR3L SDRAM power-supply.

Variants Currently in Production

 TE0726 VariantZynq SoC

RAM

FlashEthernetTemperature Range
TE0726-03RXC7Z010-1CLG225C128 MByte16 MByte-Commercial grade
TE0726-03MXC7Z010-1CLG225C512 MByte16 MByte10/100 MbitCommercial grade
TE0726-03-07S-1CXC7Z007S-1CLG225C512 MByte16 MByte10/100 MbitCommercial grade

Technical Specifications

 

If TE0726 module is powered by micro-USB connector J1 VBUS pin, which voltage level is controlled by supplying host according to the USB standards and should be 5V, there is not much user can control here if using standard USB equipment. However, user can also power the module by applying voltage to the J5 connector from other external sources. In both cases following maximum voltage ratings apply.

Absolute Maximum Ratings

Parameter

MinMax

Units

Notes

Power supply voltage

J1: USB_V_BUS, J5: 5V

4.75

5.25

V

-
VOUT of AP2152SG-13-VIN + 0.3VOutput voltage.
ILOAD of AP2152SG-13-Internal limitedAMaximum continuous load current.
PS MIO supply voltage-0.53.6VSee Xilinx DS187 datasheet
PS MIO input voltage-0.4VCCO_MIO + 0.55VVCCO_MIO0_500 and VCCO_MIO1_501.
PL HR I/O banks supply voltage-0.53.6VSee Xilinx DS187 datasheet
PL HR I/O banks input voltage-0.4VCCO + 0.55VSee Xilinx DS187 datasheet

Storage temperature

-55

+125

°C

-

See also the Xilinx datasheet DS187 for more information about absolute maximum ratings.

Recommended Operating Conditions

Normally TE0726 module is powered by micro-USB connector J1 VBUS pin, which voltage level is controlled by host according to the USB standards and should be 5V, so there is not much user can control here if using standard USB equipment.

...

ParameterMinMaxUnitsNotes

Power supply voltage

2.7

J1: USB_V_BUS, J5: 5V

4.75

5.5VSee AP2152SG-13 datasheet.
IOUT of AP2152SG-130500mA-
PS MIO supply voltage1.713.465
5.5
VSee
AP2152SG-13 datasheet. Not applicable if TE0726 module is powered by micro-USB connector J1 as VBUS pin voltage level of 5V is controlled by the supplying side equipment.

Storage temperature

-55

+125

°C

-

Recommended Operating Conditions

Xilinx DS187 datasheet
PS MIO input voltage-0.2VCCO_MIO + 0.2VVCCO_MIO0_500 and VCCO_MIO1_501.
PL HR I/O banks supply voltage1.143.465VSee Xilinx DS187 datasheet
PL HR I/O banks input voltage-0.2VCCO + 0.2VSee Xilinx DS187 datasheet
ParameterMinMaxUnitsNotesPower supply voltage

4.8

5.3VSee AP2152SG-13 datasheet.
Operating temperature070

°C

-
See LAN9514 datasheet.

The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Page break

Physical Dimensions

  • Module size: 40 mm × 30 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm

  • PCB thickness: 1.6 mm

  • Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.

...

Date

Revision

Contributors

Description

2017-0511-2410



John HartfielWeight.
  • rework J8 header
2017-11-10v.51Ali Naseri
  • Updated Power section
  • added Power-Distribution diagram
2017-05-30

v.40


Jan Kumann
  • Absolute maximum ratings
  • Layout redesign
  • Wiki link fixed
  • SoC model removed from BD

2017-05-24

V.1V1

Jan Kumann

  • Initial version.

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