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BankZynq PinNameConnected To
34G14PUDCJumper J14
35G15DSI_XASystem Controller CPLD, pin 16
35F15DSI_XBSystem Controller CPLD, pin 17

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Header J8 Interface Mapping

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26 PL IO  and 2 MIO IOs over I2C mux. All Bank IO voltages are 3.3V.

J8 Pin
 
Name
GPIO
Zynq Pin
Zynq PinNameJ8 Pin
GPIO2
1
K15
3.3V
 
-
GPIO15

-
N13
5V
10
2
GPIO3
3
J14
GPIO2
5
K15
 

-
GPIO16
5V
L13
4
36
5
GPIO4
GPIO3
H12
J14
7

-
 
GND
GPIO17
6
G11
7
11
GPIO4
GPIO5
H12
N14

M12
29
GPIO14
 
8
GPIO18
9
H11
GND
12
-
GPIO6

N13
R15
GPIO15
31
10
 
11
GPIO19
GPIO17
R12
G11
35

H11
GPIO7
GPIO18
L14
12
26
13
 
GPIO27
GPIO20
G12
M14

-
38
GND
GPIO8
14
L15
15
24
GPIO22
 
H13
GPIO21

J11
P15
GPIO23
40
16
GPIO9
17
J13
3.3V
21
-
 

K11
GPIO22
GPIO24
H13
18
15
19
GPIO1916
GPIO10H14
19 GPIO23J11

-GND20
21GPIO9J13
K13GPIO2522
23GPIO11J15
23 GPIO24K1118GPIO12M1532 GPIO25K1322GPIO13R1333 

L15GPIO824
25GND-
L14GPIO726
27MIO49(ID_SDA via TCA9544APWR) 
 MIO48 (ID_SCL via TCA9544APWR )28
29GPIO5N14
-GND30
31GPIO6R15
M15GPIO1232
33GPIO13R13
-GND34
35GPIO19R12
L13GPIO1636
37GPIO26L12
37

M14GPIO20
GPIO14
38
M12
39
8
GND
 
-
GPIO27

P15
G12
GPIO21
13
40

Page break

Default MIO Mapping

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Date

Revision

Contributors

Description

2017-11-10



John Hartfiel
  • rework J8 header
2017-11-10v.51Ali Naseri
  • Updated Power section
,
  • added Power-Distribution diagram
.
2017-05-30

V3v.40


Jan Kumann
  • Absolute maximum ratings
.
  • Layout redesign
.
  • Wiki link fixed
.
  • SoC model removed from BD
.
2017-05-24

V2

John HartfielWeight.

2017-05-24

V1

Jan Kumann

  • Initial version.

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