Page History
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| FPGA Bank | Zynq Pin | Signal Name | Connected To | ||||
|---|---|---|---|---|---|---|---|
| 34 | G14 | PUDC | Jumper J14 | 34 | M10 | CSI_D0_P | CSI-2 camera connector J3 |
| 34 | M11 | CSI_D0_N | CSI-2 camera connector J3 | ||||
| 34 | P13 | CSI_D1_P | CSI-2 camera connector J3 | ||||
| 34 | P14 | CSI_D1_N | CSI-2 camera connector J3 | ||||
| 34 | N11 | CSI_C_P | CSI-2 camera connector J3 | ||||
| 34 | N12 | CSI_C_N | CSI-2 camera connector J3 |
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Signal Name | Clock IC | Default Frequency | Destination IC | Pin | Notes |
|---|---|---|---|---|---|
| PS_CLK | U14 | 33.333333 MHz | U1 | C7 | Zynq SoC system reference clock. |
| OSCI | U7 | 12.000000 MHz | U3 | 3 | FT2232H oscillator input. |
| CLK24M | U2 | 24 MHz (see also REFSEL0 .. 2) | U18 | 26 | Reference input/output clock, see datasheet. |
| CLK25M | U13 | 25.000000 MHz | U2 | 61 | External 25 MHz crystal input. |
Hi-speed USB 2.0 and 10/100 Mbit Ethernet
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The TE0726-03 has on-board SMSC LAN9514 controller featuring USB 2.0 hub and 10/100 Mbit Ethernet controller. USB hub has four downstream ports and one upstream port, fully compliant with Universal Serial Bus Specification Revision 2.0. HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) compatible. Upstream port is connected to the SMSC USB3320 hi-speed USB 2.0 ULPI transceiver which has full support for the optional On-The-Go (OTG) protocol.
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Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-05-24 | John Hartfiel | Weight. | |
2017-05-24 | V.1 | Jan Kumann | Initial version. |
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Overview
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