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Table 4: LED's functionality
Header place-holder J4
The place-holder J4 with solder-pads to mount a 2-row 10-pin header provides the capability, to access via this header the SDIO-port of the mounted 4 x 5 SoM, if available. For this purpose, there is also voltage-translation via SDIO port expander (e.g. Texas Instruments TXS02612) necessary due to the different voltage levels of the Micro SD Card (3.3V) and MIO0-bank of the Xilinx Zynq-chip (1.8V).
In other cases the connector J4 can be used to access the PL IO-bank-pins of the SoM.
Place holders for optional pin-headers
The TEBA0841 base-board has place-holders with solder-pads to mount optional pin-headers capable to access the PL IO-bank pins of the mounted 4 x 5 SoM. With mounted pin-headers SoM's IO's are available to the userthis user interfaces, a large quantity of these IO's are also usable as as LVDS-pairs . This pin-headers provide also VCCIO voltages and different VCCIO's are available to operate the IO's properly.
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| Connector Designator | Pin-header Layout | Count of IO's | Count of LVDS-pairs | Available VCCIO's | Interfaces |
|---|---|---|---|---|---|
| J4 | 2-row 10-pin | 6 | 0 | 3.3V M1.8VOUT (from mounted module) | SDIO (6 IO's allocated), if available on mounted 4 x 5 SoM. Voltagevoltage-translation via SDIO port expander (e.g. Texas Instruments TXS02612) necessary |
| J17 | 2-row 50-pin | 42 (Bank 13) | 21 | 3.3V VCCIOD | - |
| J20 | 2-row 50-pin | 42 (Bank 35) | 21 | 3.3V VCCIOA | - |
| J3 | 2-row 16-pin | 12 | 1 | 3.3V | JTAG (4 IO's allocated). UART (2 IO's allocated). Reference clock input MGT-CLK0 (1 LVDS-pair). |
Table 5: Summary of optional pin-headers
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