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Connector DesignatorPin-header LayoutCount of IO'sCount of LVDS-pairsAvailable VCCIO'sInterfaces
J42-row 10-pin60

3.3V,
M1.8VOUT (from mounted module)

SDIO (6 IO's allocated), if available on mounted 4 x 5 SoM.

Voltage-translation via SDIO port expander (e.g. Texas Instruments TXS02612) necessary
due to the different voltage levels of the Micro SD Card (3.3V) and MIO0-bank of the Xilinx Zynq-chip (1.8V).

J172-row 50-pin42 (Bank 13)21

3.3V,
VCCIOD

-
J202-row 50-pin42 (Bank 35)21

3.3V;

VCCIOA

-
J32-row 16-pin121

3.3V

JTAG (4 IO's allocated).

UART (2 IO's allocated).

Reference clock input MGT-CLK0 (1 LVDS-pair).

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