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The JTAG-interface of the mounted 4 x 5 SoM can be accessed via header JX1 or J3 with , which has two additional pins (15,16) as LVDS-pair to supply the mounted 4 x 5 SoM with an external reference clock-signal.

This header has The headers JX1 and J3 have a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment, so in use with the XMOD-FT2232H adapter-board TE0790 can be used in conjunction with the carrier board to program the mounted SoM can be programmed via USB interface.

JX1 pinJX1 pin Schematic NameB2B J3 pinJ3 pin Schematic NameB2B
C (pin 4)TCKJB3-100 4TCKJB3-100
D (pin 8)TDOJB3-98 8TDOJB3-98
F (pin 10)TDIJB3-96 10TDIJB3-96
H (pin 12)TMSJB3-94 12TMSJB3-94
A (pin 3)MIO15JB1-86 (usable as UART RX/TX-line) 3MIO15JB1-86 (usable as UART RX/TX-line)
B (pin 7)MIO14JB1-91 (usable as UART RX/TX-line) 7MIO14JB1-91 (usable as UART RX/TX-line)
E (pin 9)BOOTMODEJB1-90 (JTAGSELECT) 9BOOTMODEJB1-90 (JTAGSELECT)
G (pin 11)RESINJB3-17 11RESINJB3-17
--- 15CLK0_NJB2-32 (MGT_CLK0_N, decoupling capacitator 100 nF)
--- 16CLK0_PJB2-34 (MGT_CLK0_P, decoupling capacitator 100 nF)

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Following table describes how to configure the base-board supply-voltages by jumpers:

Base-board Supply Voltages
vs Voltage-levels

VCCIOAVCCIOD
1.8VJ26:1-2J27:1-2
2.5VJ26:3-4J27:3-4
3.3VJ26:5-6J27:5-6

Table 6: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2' means pins 1 and 2 are connected, 'Jx: 3-4' means pins 3 and 4 are connected, and so on.

Note

Take care of the VCCO voltage ranges of the  particular PL IO-banks (HR, HP) of the mounted SoM, otherwise damages may occur to the FPGA. Therefore, refer to the TRM of the mounted SoM to get the specific information of the voltage ranges.

It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4 x 5 module to avoid failures and damages to the functionality of the mounted SoM.

 

Technical Specifications

Absolute Maximum Ratings

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